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altera corporation 1 flex 10k embedded programmable logic family may 2000, ver. 4.02 data sheet a-ds-f10k-04.02 includes flex 10ka features... the industry? first embedded programmable logic device (pld) family, providing system-on-a-programmable-chip tm integration embedded array for implementing megafunctions, such as efficient memory and specialized logic functions logic array for general logic functions high density 10,000 to 250,000 typical gates (see tables 1 and 2 ) up to 40,960 ram bits; 2,048 bits per embedded array block (eab), all of which can be used without reducing logic capacity system-level features multivolt tm i/o interface support 5.0-v tolerant input pins in flex 10ka devices low power consumption (typical specification less than 0.5 ma in standby mode for most devices) flex 10k and flex 10ka devices support peripheral component interconnect special interest group (pci sig) pci local bus specification, revision 2.2 flex 10ka devices include pull-up clamping diode, selectable on a pin-by-pin basis for 3.3-v pci compliance select flex 10ka devices support 5.0-v pci buses with eight or fewer loads built-in joint test action group (jtag) boundary-scan test (bst) circuitry compliant with ieee std. 1149.1-1990, available without consuming any device logic table 1. flex 10k device features feature epf10k10 epf10k10a epf10k20 epf10k30 epf10k30a epf10k40 epf10k50 epf10k50v typical gates (logic and ram) (1) 10,000 20,000 30,000 40,000 50,000 maximum system gates 31,000 63,000 69,000 93,000 116,000 logic elements (les) 576 1,152 1,728 2,304 2,880 logic array blocks (labs) 72 144 216 288 360 embedded array blocks (eabs) 366810 total ram bits 6,144 12,288 12,288 16,384 20,480 maximum user i/o pins 150 189 246 189 310
2 altera corporation flex 10k embedded programmable logic family data sheet note to tables: (1) the embedded ieee std. 1149.1 jtag circuitry adds up to 31,250 gates in addition to the listed typical or maximum system gates. ...and more features devices are fabricated on advanced processes and operate with a 3.3-v or 5.0-v supply voltage (see table 3 ) in-circuit reconfigurability (icr) via external configuration device, intelligent controller, or jtag port clocklock tm and clockboost tm options for reduced clock delay/skew and clock multiplication built-in low-skew clock distribution trees 100 % functional testing of all devices; test vectors or scan chains are not required table 2. flex 10k device features feature epf10k70 epf10k100 epf10k100a epf10k130v epf10k250a typical gates (logic and ram) (1) 70,000 100,000 130,000 250,000 maximum system gates 118,000 158,000 211,000 310,000 les 3,744 4,992 6,656 12,160 labs 468 624 832 1,520 eabs 9 12 16 20 total ram bits 18,432 24,576 32,768 40,960 maximum user i/o pins 358 406 470 470 table 3. supply voltages for flex 10k & flex 10ka devices 5.0-v devices 3.3-v devices epf10k10 epf10k20 epf10k30 epf10k40 epf10k50 epf10k70 epf10k100 epf10k10a epf10k30a epf10k50v epf10k100a epf10k130v epf10k250a
altera corporation 3 flex 10k embedded programmable logic family data sheet flexible interconnect fasttrack interconnect continuous routing structure for fast, predictable interconnect delays dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators (automatically used by software tools and megafunctions) dedicated cascade chain that implements high-speed, high-fan-in logic functions (automatically used by software tools and megafunctions) tri-state emulation that implements internal tri-state buses up to six global clock signals and four global clear signals powerful i/o pins individual tri-state output enable control for each pin open-drain option on each i/o pin programmable output slew-rate control to reduce switching noise flex 10ka devices support hot-socketing peripheral register for fast setup and clock-to-output delay flexible package options available in a variety of packages with 84 to 600 pins (see table 4 ) pin-compatibility with other flex 10k devices in the same package fineline bga tm packages maximize board space efficiency software design support and automatic place-and-route provided by altera? max+plus ? ii development system for windows-based pcs and sun sparcstation, hp 9000 series 700/800, and ibm risc system/6000 workstations, and quartus tm development system for windows-based pcs and sun sparcstation and hp 9000 series 700 workstations additional design entry and simulation support provided by edif 2 0 0 and 3 0 0 netlist files, library of parameterized modules (lpm), designware components, verilog hdl, vhdl, and other interfaces to popular eda tools from manufacturers such as cadence, exemplar logic, mentor graphics, orcad, synopsys, synplicity, veribest, and viewlogic
4 altera corporation flex 10k embedded programmable logic family data sheet table 4. flex 10k plcc, tqfp, pqfp, rqfp & pga package options & i/o pin count notes (1) , (2) device 84-pin plcc 100-pin tqfp 144-pin tqfp 208-pin pqfp rqfp 240-pin pqfp rqfp 403-pin pga epf10k10 59 102 134 epf10k10a 66 102 134 epf10k20 102 147 189 epf10k30 147 189 epf10k30a 102 147 189 epf10k40 147 189 epf10k50 189 310 epf10k50v 189 epf10k70 189 epf10k100 epf10k100a 189 epf10k130v epf10k250a table 5. flex 10k bga & fineline bga package options & i/o pin count notes (1) , (2) device 503-pin pga 599-pin pga 256-pin fineline bga 356-pin bga 484-pin fineline bga 600-pin bga epf10k10 epf10k10a 150 150 (3) epf10k20 epf10k30 246 epf10k30a 191 246 246 epf10k40 epf10k50 274 epf10k50v 274 291 epf10k70 358 epf10k100 406 epf10k100a 274 369 406 epf10k130v 470 470 epf10k250a 470 470
altera corporation 5 flex 10k embedded programmable logic family data sheet notes to tables: (1) contact altera customer marketing for up-to-date information on package availability. (2) flex 10k and flex 10ka device package types include plastic j-lead chip carrier (plcc), thin quad flat pack (tqfp), plastic quad flat pack (pqfp), power quad flat pack (rqfp), ball-grid array (bga), pin-grid array (pga), and fineline bga tm packages. (3) this option will be supported with a 256-pin fineline bga package. by using sameframe pin migration, all fineline bga packages are pin compatible. for example, a board can be designed to support both 256-pin and 484-pin fineline bga packages. the quartus and max+plus ii software automatically avoids conflicting pins when future migration is set. general description altera? flex 10k devices are the industry? first embedded plds. based on reconfigurable cmos sram elements, the flexible logic element matrix (flex) architecture incorporates all features necessary to implement common gate array megafunctions. with up to 250,000 gates, the flex 10k family provides the density, speed, and features to integrate entire systems, including multiple 32-bit buses, into a single device. flex 10k devices are reconfigurable, which allows 100 % testing prior to shipment. as a result, the designer is not required to generate test vectors for fault coverage purposes. additionally, the designer does not need to manage inventories of different asic designs; flex 10k devices can be configured on the board for the specific functionality required. table 6 shows flex 10k performance for some common designs. all performance values were obtained with synopsys designware or lpm functions. no special design technique was required to implement the applications; the designer simply inferred or instantiated a function in a verilog hdl, vhdl, altera hardware description language (ahdl), or schematic design file. notes: (1) the speed grade of this application is limited because of clock high and low specifications. (2) this application uses combinatorial inputs and outputs. (3) this application uses registered inputs and outputs. table 6. flex 10k & flex 10ka performance application resources used performance units speed grade les eabs -1 -2 -3 -4 16-bit loadable counter (1) 16 0 204 166 125 95 mhz 16-bit accumulator (1) 16 0 204 166 125 95 mhz 16-to-1 multiplexer (2) 10 0 4.2 5.8 6.0 7.0 ns 256 8 ram read cycle speed (3) 0 1 172 145 108 84 mhz 256 8 ram write cycle speed (3) 0 1 106 89 68 63 mhz
6 altera corporation flex 10k embedded programmable logic family data sheet the flex 10k architecture is similar to that of embedded gate arrays, the fastest-growing segment of the gate array market. as with standard gate arrays, embedded gate arrays implement general logic in a conventional ?ea-of-gates?architecture. in addition, embedded gate arrays have dedicated die areas for implementing large, specialized functions. by embedding functions in silicon, embedded gate arrays provide reduced die area and increased speed compared to standard gate arrays. however, embedded megafunctions typically cannot be customized, limiting the designer? options. in contrast, flex 10k devices are programmable, providing the designer with full control over embedded megafunctions and general logic while facilitating iterative design changes during debugging. each flex 10k device contains an embedded array and a logic array. the embedded array is used to implement a variety of memory functions or complex logic functions, such as digital signal processing (dsp), microcontroller, wide-data-path manipulation, and data-transformation functions. the logic array performs the same function as the sea-of-gates in the gate array: it is used to implement general logic, such as counters, adders, state machines, and multiplexers. the combination of embedded and logic arrays provides the high performance and high density of embedded gate arrays, enabling designers to implement an entire system on a single device. flex 10k devices are configured at system power-up with data stored in an altera serial configuration device or provided by a system controller. altera offers the epc2, epc1, and epc1441 configuration devices, which configure flex 10k devices via a serial data stream. configuration data can also be downloaded from system ram or from altera? bitblaster tm serial download cable, byteblaster tm parallel port download cable, or byteblastermv tm parallel port download cable (the byteblaster cable is obsolete and is replaced by the byteblastermv cable, which can program or configure 2.5-v, 3.3-v, and 5.0-v devices). after a flex 10k device has been configured, it can be reconfigured in-circuit by resetting the device and loading new data. because reconfiguration requires less than 320 ms, real-time changes can be made during system operation. flex 10k devices contain an optimized interface that permits microprocessors to configure flex 10k devices serially or in parallel, and synchronously or asynchronously. the interface also enables microprocessors to treat a flex 10k device as memory and configure the device by writing to a virtual memory location, making it very easy for the designer to reconfigure the device.
altera corporation 7 flex 10k embedded programmable logic family data sheet f for more information, see the following documents: configuration devices for apex & flex devices data sheet bitblaster serial download cable data sheet byteblaster parallel port download cable data sheet byteblastermv parallel port download cable data sheet application note 59 (configuring flex 10k devices) flex 10k devices are supported by quartus and max+plus ii development systems; a single, integrated package that offers schematic, text (including ahdl), and waveform design entry, compilation and logic synthesis, full simulation and worst-case timing analysis, and device configuration. the quartus and max+plus ii software provides edif 2 0 0 and 3 0 0, lpm, vhdl, verilog hdl, and other interfaces for additional design entry and simulation support from other industry- standard pc- and unix workstation-based eda tools. the quartus and max+plus ii software works easily with common gate array eda tools for synthesis and simulation. for example, the max+plus ii software can generate verilog hdl files for simulation with tools such as cadence verilog-xl. additionally, the quartus and max+plus ii software contains eda libraries that use device-specific features such as carry chains which are used for fast counter and arithmetic functions. for instance, the synopsys design compiler library supplied with the quartus and max+plus ii development systems include designware functions that are optimized for the flex 10k architecture. the max+plus ii development system runs on windows-based pcs and sun sparcstation, hp 9000 series 700/800, and ibm risc system/6000 workstations, and the quartus development system runs on windows- based pcs and sun sparcstation and hp 9000 series 700 workstations. f see the max+plus ii programmable logic development system & software data sheet for more information. functional description each flex 10k device contains an embedded array to implement memory and specialized logic functions, and a logic array to implement general logic. the embedded array consists of a series of eabs. when implementing memory functions, each eab provides 2,048 bits, which can be used to create ram, rom, dual-port ram, or first-in first-out (fifo) functions. when implementing logic, each eab can contribute 100 to 600 gates towards complex logic functions, such as multipliers, microcontrollers, state machines, and dsp functions. eabs can be used independently, or multiple eabs can be combined to implement larger functions.
8 altera corporation flex 10k embedded programmable logic family data sheet the logic array consists of logic array blocks (labs). each lab contains eight les and a local interconnect. an le consists of a 4-input look-up table (lut), a programmable flipflop, and dedicated signal paths for carry and cascade functions. the eight les can be used to create medium-sized blocks of logic?-bit counters, address decoders, or state machines?r combined across labs to create larger logic blocks. each lab represents about 96 usable gates of logic. signal interconnections within flex 10k devices and to and from device pins are provided by the fasttrack interconnect, a series of fast, continuous row and column channels that run the entire length and width of the device. each i/o pin is fed by an i/o element (ioe) located at the end of each row and column of the fasttrack interconnect. each ioe contains a bidirectional i/o buffer and a flipflop that can be used as either an output or input register to feed input, output, or bidirectional signals. when used with a dedicated clock pin, these registers provide exceptional performance. as inputs, they provide setup times as low as 1.6 ns and hold times of 0 ns; as outputs, these registers provide clock-to-output times as low as 5.3 ns. ioes provide a variety of features, such as jtag bst support, slew-rate control, tri-state buffers, and open-drain outputs. figure 1 shows a block diagram of the flex 10k architecture. each group of les is combined into an lab; labs are arranged into rows and columns. each row also contains a single eab. the labs and eabs are interconnected by the fasttrack interconnect. ioes are located at the end of each row and column of the fasttrack interconnect.
altera corporation 9 flex 10k embedded programmable logic family data sheet figure 1. flex 10k device block diagram flex 10k devices provide six dedicated inputs that drive the flipflops? control inputs to ensure the efficient distribution of high-speed, low-skew (less than 1.5 ns) control signals. these signals use dedicated routing channels that provide shorter delays and lower skews than the fasttrack interconnect. four of the dedicated inputs drive four global signals. these four global signals can also be driven by internal logic, providing an ideal solution for a clock divider or an internally generated asynchronous clear signal that clears many registers in the device. embedded array block the eab is a flexible block of ram with registers on the input and output ports, and is used to implement common gate array megafunctions. the eab is also suitable for functions such as multipliers, vector scalars, and error correction circuits, because it is large and flexible. these functions can be combined in applications such as digital filters and microcontrollers. i/o element (ioe) logic array block (lab) row interconnect ioe ioe ioe ioe ioe ioe ioe local interconnect ioe ioe ioe ioe ioe ioe ioe ioe ioe ioe logic element (le) column interconnect ioe eab eab logic array ioe ioe ioe ioe ioe ioe embedded array block (eab) embedded array ioe ioe logic array ioe ioe
10 altera corporation flex 10k embedded programmable logic family data sheet logic functions are implemented by programming the eab with a read- only pattern during configuration, creating a large lut. with luts, combinatorial functions are implemented by looking up the results, rather than by computing them. this implementation of combinatorial functions can be faster than using algorithms implemented in general logic, a performance advantage that is further enhanced by the fast access times of eabs. the large capacity of eabs enables designers to implement complex functions in one logic level without the routing delays associated with linked les or field-programmable gate array (fpga) ram blocks. for example, a single eab can implement a 4 4 multiplier with eight inputs and eight outputs. parameterized functions such as lpm functions can automatically take advantage of the eab. the eab provides advantages over fpgas, which implement on-board ram as arrays of small, distributed ram blocks. these fpga ram blocks contain delays that are less predictable as the size of the ram increases. in addition, fpga ram blocks are prone to routing problems because small blocks of ram must be connected together to make larger blocks. in contrast, eabs can be used to implement large, dedicated blocks of ram that eliminate these timing and routing concerns. eabs can be used to implement synchronous ram, which is easier to use than asynchronous ram. a circuit using asynchronous ram must generate the ram write enable ( we ) signal, while ensuring that its data and address signals meet setup and hold time specifications relative to the we signal. in contrast, the eab? synchronous ram generates its own we signal and is self-timed with respect to the global clock. a circuit using the eab? self-timed ram need only meet the setup and hold time specifications of the global clock. when used as ram, each eab can be configured in any of the following sizes: 256 8, 512 4, 1,024 2, or 2,048 1. see figure 2 . figure 2. eab memory con?urations 256 8 512 4 1,024 2 2,048 1
altera corporation 11 flex 10k embedded programmable logic family data sheet larger blocks of ram are created by combining multiple eabs. for example, two 256 8 ram blocks can be combined to form a 256 16 ram block; two 512 4 blocks of ram can be combined to form a 512 8 ram block. see figure 3 . figure 3. examples of combining eabs if necessary, all eabs in a device can be cascaded to form a single ram block. eabs can be cascaded to form ram blocks of up to 2,048 words without impacting timing. altera? max+plus ii software automatically combines eabs to meet a designer? ram specifications. eabs provide flexible options for driving and controlling clock signals. different clocks can be used for the eab inputs and outputs. registers can be independently inserted on the data input, eab output, or the address and we inputs. the global signals and the eab local interconnect can drive the we signal. the global signals, dedicated clock pins, and eab local interconnect can drive the eab clock signals. because the les drive the eab local interconnect, the les can control the we signal or the eab clock signals. each eab is fed by a row interconnect and can drive out to row and column interconnects. each eab output can drive up to two row channels and up to two column channels; the unused row channel can be driven by other les. this feature increases the routing resources available for eab outputs. see figure 4 . 512 4 512 4 256 8 256 8 256 16 512 8
12 altera corporation flex 10k embedded programmable logic family data sheet figure 4. flex 10k embedded array block note: (1) epf10k10, epf10k10a, epf10k20, epf10k30, epf10k30a, epf10k40, epf10k50, and epf10k50v devices have 22 eab local interconnect channels; epf10k70, epf10k100, epf10k100a, epf10k130v, and epf10k250a devices have 26. d dq column interconnect row interconnect ram/rom 256 8 512 4 1,024 2 2,048 1 we address data in 8, 4, 2, 1 eab local interconnect (1) dedicated inputs & global signals (1) 6 d q d q d q data out 24 chip-wide reset 8, 9, 10, 11 2, 4, 8, 16 2, 4, 8, 16
altera corporation 13 flex 10k embedded programmable logic family data sheet logic array block each lab consists of eight les, their associated carry and cascade chains, lab control signals, and the lab local interconnect. the lab provides the coarse-grained structure to the flex 10k architecture, facilitating efficient routing with optimum device utilization and high performance. see figure 5 . figure 5. flex 10k lab notes: (1) epf10k10, epf10k10a, epf10k20, epf10k30, epf10k30a, epf10k40, epf10k50, and epf10k50v devices have 22 inputs to the lab local interconnect channel from the row; epf10k70, epf10k100, epf10k100a, epf10k130v, and epf10k250a devices have 26. (2) epf10k10, epf10k10a, epf10k20, epf10k30, epf10k30a, epf10k40, epf10k50, and epf10k50v devices have 30 lab local interconnect channels; epf10k70, epf10k100, epf10k100a, epf10k130v, and epf10k250a devices have 34 labs. 2 8 carry-in & cascade-in le1 le8 le2 le3 le4 le5 le6 le7 column interconnect row interconnect (1) lab local interconnect (2) column-to-row interconnect carry-out & cascade-out 16 24 lab control signals see figure 11 for details. 6 dedicated inputs & global signals 16 4 8 4 4 4 4 4 4 4 4 4 4 2 8
14 altera corporation flex 10k embedded programmable logic family data sheet each lab provides four control signals with programmable inversion that can be used in all eight les. two of these signals can be used as clocks; the other two can be used for clear/preset control. the lab clocks can be driven by the dedicated clock input pins, global signals, i/o signals, or internal signals via the lab local interconnect. the lab preset and clear control signals can be driven by the global signals, i/o signals, or internal signals via the lab local interconnect. the global control signals are typically used for global clock, clear, or preset signals because they provide asynchronous control with very low skew across the device. if logic is required on a control signal, it can be generated in one or more les in any lab and driven into the local interconnect of the target lab. in addition, the global control signals can be generated from le outputs. logic element the le, the smallest unit of logic in the flex 10k architecture, has a compact size that provides efficient logic utilization. each le contains a four-input lut, which is a function generator that can quickly compute any function of four variables. in addition, each le contains a programmable flipflop with a synchronous enable, a carry chain, and a cascade chain. each le drives both the local and the fasttrack interconnect. see figure 6 . figure 6. flex 10k logic element to lab local interconnect carry-in clock select carry-out look-up table (lut) clear/ preset logic carry chain cascade chain cascade-in cascade-out to fasttrack interconnect programmable register prn clrn dq ena register bypass chip-wide reset data1 data2 data3 data4 labctrl1 labctrl2 labctrl3 labctrl4
altera corporation 15 flex 10k embedded programmable logic family data sheet the programmable flipflop in the le can be configured for d, t, jk, or sr operation. the clock, clear, and preset control signals on the flipflop can be driven by global signals, general-purpose i/o pins, or any internal logic. for combinatorial functions, the flipflop is bypassed and the output of the lut drives the output of the le. the le has two outputs that drive the interconnect; one drives the local interconnect and the other drives either the row or column fasttrack interconnect. the two outputs can be controlled independently. for example, the lut can drive one output while the register drives the other output. this feature, called register packing, can improve le utilization because the register and the lut can be used for unrelated functions. the flex 10k architecture provides two types of dedicated high-speed data paths that connect adjacent les without using local interconnect paths: carry chains and cascade chains. the carry chain supports high- speed counters and adders; the cascade chain implements wide-input functions with minimum delay. carry and cascade chains connect all les in an lab and all labs in the same row. intensive use of carry and cascade chains can reduce routing flexibility. therefore, the use of these chains should be limited to speed-critical portions of a design. carry chain the carry chain provides a very fast (as low as 0.2 ns) carry-forward function between les. the carry-in signal from a lower-order bit drives forward into the higher-order bit via the carry chain, and feeds into both the lut and the next portion of the carry chain. this feature allows the flex 10k architecture to implement high-speed counters, adders, and comparators of arbitrary width efficiently. carry chain logic can be created automatically by the quartus and max+plus ii compilers during design processing, or manually by the designer during design entry. parameterized functions such as lpm and designware functions automatically take advantage of carry chains. carry chains longer than eight les are automatically implemented by linking labs together. for enhanced fitting, a long carry chain skips alternate labs in a row. a carry chain longer than one lab skips either from even-numbered lab to even-numbered lab, or from odd- numbered lab to odd-numbered lab. for example, the last le of the first lab in a row carries to the first le of the third lab in the row. the carry chain does not cross the eab at the middle of the row. for instance, in the epf10k50 device, the carry chain stops at the eighteenth lab and a new one begins at the nineteenth lab.
16 altera corporation flex 10k embedded programmable logic family data sheet figure 7 shows how an n -bit full adder can be implemented in n + 1 les with the carry chain. one portion of the lut generates the sum of two bits using the input signals and the carry-in signal; the sum is routed to the output of the le. the register can either be bypassed for simple adders or be used for an accumulator function. the carry chain logic generates the carry-out signal, which is routed directly to the carry-in signal of the next- higher-order bit. the final carry-out signal is routed to an le, where it can be used as a general-purpose signal. figure 7. carry chain operation (n-bit full adder) lut a1 b1 carry chain s1 le1 register a2 b2 carry chain s2 le2 register carry chain s n le n register a n b n carry chain carry-out le n + 1 register carry-in lut lut lut
altera corporation 17 flex 10k embedded programmable logic family data sheet cascade chain with the cascade chain, the flex 10k architecture can implement functions that have a very wide fan-in. adjacent luts can be used to compute portions of the function in parallel; the cascade chain serially connects the intermediate values. the cascade chain can use a logical and or logical or (via de morgan? inversion) to connect the outputs of adjacent les. each additional le provides four more inputs to the effective width of a function, with a delay as low as 0.7 ns per le. cascade chain logic can be created automatically by the max+plus ii compiler during design processing, or manually by the designer during design entry. cascade chains longer than eight bits are implemented automatically by linking several labs together. for easier routing, a long cascade chain skips every other lab in a row. a cascade chain longer than one lab skips either from even-numbered lab to even-numbered lab, or from odd-numbered lab to odd-numbered lab (e.g., the last le of the first lab in a row cascades to the first le of the third lab). the cascade chain does not cross the center of the row (e.g., in the epf10k50 device, the cascade chain stops at the eighteenth lab and a new one begins at the nineteenth lab). this break is due to the eab? placement in the middle of the row. figure 8 shows how the cascade function can connect adjacent les to form functions with a wide fan-in. these examples show functions of 4 n variables implemented with n les. the le delay is as low as 1.6 ns; the cascade chain delay is as low as 0.7 ns. with the cascade chain, 3.7 ns is needed to decode a 16-bit address. figure 8. cascade chain operation le1 lut le2 lut d[3..0] d[7..4] d[(4 n -1)..(4 n -4)] d[3..0] d[7..4] d[(4 n -1)..(4 n -4)] le n le1 le2 le n lut lut lut lut and cascade chain or cascade chain
18 altera corporation flex 10k embedded programmable logic family data sheet le operating modes the flex 10k le can operate in the following four modes: normal mode arithmetic mode up/down counter mode clearable counter mode each of these modes uses le resources differently. in each mode, seven available inputs to the le?he four data inputs from the lab local interconnect, the feedback from the programmable register, and the carry-in and cascade-in from the previous le?re directed to different destinations to implement the desired logic function. three inputs to the le provide clock, clear, and preset control for the register. quartus and max+plus ii software packages, in conjunction with parameterized functions such as lpm and designware functions, automatically chooses the appropriate mode for common functions such as counters, adders, and multipliers. if required, the designer can also create special-purpose functions which use a specific le operating mode for optimal performance. the architecture provides a synchronous clock enable to the register in all four modes. quartus and max+plus ii software packages can set data1 to enable the register synchronously, providing easy implementation of fully synchronous designs. figure 9 shows the le operating modes.
altera corporation 19 flex 10k embedded programmable logic family data sheet figure 9. flex 10k le operating modes note: (1) packed registers cannot be used with the cascade chain. ena prn clrn dq 4-input lut carry-in cascade-out cascade-in (1) le-out to fasttrack interconnect le-out to local interconnect ena normal mode prn clrn dq cascade-out le-out cascade-in 3-input lut carry-in 3-input lut carry-out arithmetic mode up/down counter mode data1 (ena) data2 (u/d) prn clrn d q 3-input lut carry-in cascade-in le-out 3-input lut carry-out data3 (data) data4 (nload) 1 0 cascade-out clearable counter mode data1 (ena) data2 (nclr) prn clrn dq 3-input lut carry-in le-out 3-input lut carry-out data3 (data) data4 (nload) 1 0 cascade-out ena ena data1 data2 data3 data4 data1 data2
20 altera corporation flex 10k embedded programmable logic family data sheet normal mode the normal mode is suitable for general logic applications and wide decoding functions that can take advantage of a cascade chain. in normal mode, four data inputs from the lab local interconnect and the carry-in are inputs to a 4-input lut. the max+plus ii compiler automatically selects the carry-in or the data3 signal as one of the inputs to the lut. the lut output can be combined with the cascade-in signal to form a cascade chain through the cascade-out signal. either the register or the lut can be used to drive both the local interconnect and the fasttrack interconnect at the same time. the lut and the register in the le can be used independently; this feature is known as register packing. to support register packing, the le has two outputs; one drives the local interconnect and the other drives the fasttrack interconnect. the data4 signal can drive the register directly, allowing the lut to compute a function that is independent of the registered signal; a 3-input function can be computed in the lut, and a fourth independent signal can be registered. alternatively, a 4-input function can be generated, and one of the inputs to this function can be used to drive the register. the register in a packed le can still use the clock enable, clear, and preset signals in the le. in a packed le, the register can drive the fasttrack interconnect while the lut drives the local interconnect, or vice versa. arithmetic mode the arithmetic mode offers two 3-input luts that are ideal for implementing adders, accumulators, and comparators. one lut computes a 3-input function, and the other generates a carry output. as shown in figure 9 on page 19 , the first lut uses the carry-in signal and two data inputs from the lab local interconnect to generate a combinatorial or registered output. for example, in an adder, this output is the sum of three signals: a , b , and carry-in. the second lut uses the same three signals to generate a carry-out signal, thereby creating a carry chain. the arithmetic mode also supports simultaneous use of the cascade chain. up/down counter mode the up/down counter mode offers counter enable, clock enable, synchronous up/down control, and data loading options. these control signals are generated by the data inputs from the lab local interconnect, the carry-in signal, and output feedback from the programmable register. two 3-input luts are used: one generates the counter data, and the other generates the fast carry bit. a 2-to-1 multiplexer provides synchronous loading. data can also be loaded asynchronously with the clear and preset register control signals, without using the lut resources.
altera corporation 21 flex 10k embedded programmable logic family data sheet clearable counter mode the clearable counter mode is similar to the up/down counter mode, but supports a synchronous clear instead of the up/down control. the clear function is substituted for the cascade-in signal in the up/down counter mode. two 3-input luts are used: one generates the counter data, and the other generates the fast carry bit. synchronous loading is provided by a 2-to-1 multiplexer. the output of this multiplexer is and ed with a synchronous clear signal. internal tri-state emulation internal tri-state emulation provides internal tri-stating without the limitations of a physical tri-state bus. in a physical tri-state bus, the tri-state buffers?output enable ( oe ) signals select which signal drives the bus. however, if multiple oe signals are active, contending signals can be driven onto the bus. conversely, if no oe signals are active, the bus will float. internal tri-state emulation resolves contending tri-state buffers to a low value and floating buses to a high value, thereby eliminating these problems. the max+plus ii software automatically implements tri-state bus functionality with a multiplexer. clear & preset logic control logic for the programmable register? clear and preset functions is controlled by the data3 , labctrl1 , and labctrl2 inputs to the le. the clear and preset control structure of the le asynchronously loads signals into a register. either labctrl1 or labctrl2 can control the asynchronous clear. alternatively, the register can be set up so that labctrl1 implements an asynchronous load. the data to be loaded is driven to data3 ; when labctrl1 is asserted, data3 is loaded into the register. during compilation, the quartus and max+plus ii compilers automatically select the best control signal implementation. because the clear and preset functions are active-low, the compiler automatically assigns a logic high to an unused clear or preset. the clear and preset logic is implemented in one of the following six modes chosen during design entry: asynchronous clear asynchronous preset asynchronous clear and preset asynchronous load with clear asynchronous load with preset asynchronous load without clear or preset
22 altera corporation flex 10k embedded programmable logic family data sheet in addition to the six clear and preset modes, flex 10k devices provide a chip-wide reset pin that can reset all registers in the device. use of this feature is set during design entry. in any of the clear and preset modes, the chip-wide reset overrides all other signals. registers with asynchronous presets may be preset when the chip-wide reset is asserted. inversion can be used to implement the asynchronous preset. figure 10 shows examples of how to enter a section of a design for the desired functionality. figure 10. le clear & preset modes asynchronous clear asynchronous preset asynchronous clear & preset asynchronous load without clear or preset prn clrn dq not not asynchronous load with clear prn clrn dq not not asynchronous load with preset not not prn clrn dq prn clrn dq vcc chip-wide reset chip-wide reset chip-wide reset chip-wide reset prn clrn dq prn clrn dq vcc chip-wide reset chip-wide reset labctrl1 or labctrl2 labctrl1 or labctrl2 labctrl1 (asynchronous load) labctrl1 (asynchronous load) labctrl1 (asynchronous load) data3 (data) labctrl2 (clear) labctrl2 (preset) data3 (data) data3 (data) labctrl2 labctrl1
altera corporation 23 flex 10k embedded programmable logic family data sheet asynchronous clear the flipflop can be cleared by either labctrl1 or labctrl2 . in this mode, the preset signal is tied to v cc to deactivate it. asynchronous preset an asynchronous preset is implemented as either an asynchronous load, or with an asynchronous clear. if data3 is tied to v cc , asserting labctrl1 asynchronously loads a one into the register. alternatively, the max+plus ii software can provide preset control by using the clear and inverting the input and output of the register. inversion control is available for the inputs to both les and ioes. therefore, if a register is preset by only one of the two labctrl signals, the data3 input is not needed and can be used for one of the le operating modes. asynchronous preset & clear when implementing asynchronous clear and preset, labctrl1 controls the preset and labctrl2 controls the clear. data3 is tied to v cc , therefore, asserting labctrl1 asynchronously loads a one into the register, effectively presetting the register. asserting labctrl2 clears the register. asynchronous load with clear when implementing an asynchronous load in conjunction with the clear, labctrl1 implements the asynchronous load of data3 by controlling the register preset and clear. labctrl2 implements the clear by controlling the register clear; labctrl2 does not have to feed the preset circuits. asynchronous load with preset when implementing an asynchronous load in conjunction with preset, the max+plus ii software provides preset control by using the clear and inverting the input and output of the register. asserting labctrl2 presets the register, while asserting labctrl1 loads the register. the max+plus ii software inverts the signal that drives data3 to account for the inversion of the register? output. asynchronous load without preset or clear when implementing an asynchronous load without preset or clear, labctrl1 implements the asynchronous load of data3 by controlling the register preset and clear.
24 altera corporation flex 10k embedded programmable logic family data sheet fasttrack interconnect in the flex 10k architecture, connections between les and device i/o pins are provided by the fasttrack interconnect, which is a series of continuous horizontal and vertical routing channels that traverse the device. this global routing structure provides predictable performance, even in complex designs. in contrast, the segmented routing in fpgas requires switch matrices to connect a variable number of routing paths, increasing the delays between logic resources and reducing performance. the fasttrack interconnect consists of row and column interconnect channels that span the entire device. each row of labs is served by a dedicated row interconnect. the row interconnect can drive i/o pins and feed other labs in the device. the column interconnect routes signals between rows and can drive i/o pins. a row channel can be driven by an le or by one of three column channels. these four signals feed dual 4-to-1 multiplexers that connect to two specific row channels. these multiplexers, which are connected to each le, allow column channels to drive row channels even when all eight les in an lab drive the row interconnect. each column of labs is served by a dedicated column interconnect. the column interconnect can then drive i/o pins or another row? interconnect to route the signals to other labs in the device. a signal from the column interconnect, which can be either the output of an le or an input from an i/o pin, must be routed to the row interconnect before it can enter an lab or eab. each row channel that is driven by an ioe or eab can drive one specific column channel. access to row and column channels can be switched between les in adjacent pairs of labs. for example, an le in one lab can drive the row and column channels normally driven by a particular le in the adjacent lab in the same row, and vice versa. this routing flexibility enables routing resources to be used more efficiently. see figure 11 .
altera corporation 25 flex 10k embedded programmable logic family data sheet figure 11. lab connections to row & column interconnect from adjacent lab row channels column channels each le can drive two row channels. le 2 le 8 le 1 to adjacent lab each le can switch interconnect access with an le in the adjacent lab. at each intersection, four row channels can drive column channels. to other rows to lab local interconnect to other columns
26 altera corporation flex 10k embedded programmable logic family data sheet for improved routing, the row interconnect is comprised of a combination of full-length and half-length channels. the full-length channels connect to all labs in a row; the half-length channels connect to the labs in half of the row. the eab can be driven by the half-length channels in the left half of the row and by the full-length channels. the eab drives out to the full-length channels. in addition to providing a predictable, row-wide interconnect, this architecture provides increased routing resources. two neighboring labs can be connected using a half-row channel, thereby saving the other half of the channel for the other half of the row. table 7 summarizes the fasttrack interconnect resources available in each flex 10k device. in addition to general-purpose i/o pins, flex 10k devices have six dedicated input pins that provide low-skew signal distribution across the device. these six inputs can be used for global clock, clear, preset, and peripheral output enable and clock enable control signals. these signals are available as control signals for all labs and ioes in the device. the dedicated inputs can also be used as general-purpose data inputs because they can feed the local interconnect of each lab in the device. however, the use of dedicated inputs as data inputs can introduce additional delay into the control signal network. table 7. flex 10k fasttrack interconnect resources device rows channels per row columns channels per column epf10k10 epf10k10a 3 144 24 24 epf10k20 6 144 24 24 epf10k30 epf10k30a 6 216 36 24 epf10k40 8 216 36 24 epf10k50 epf10k50v 10 216 36 24 epf10k70 9 312 52 24 epf10k100 epf10k100a 12 312 52 24 epf10k130v 16 312 52 32 epf10k250a 20 456 76 40
altera corporation 27 flex 10k embedded programmable logic family data sheet figure 12 shows the interconnection of adjacent labs and eabs with row, column, and local interconnects, as well as the associated cascade and carry chains. each lab is labeled according to its location: a letter represents the row and a number represents the column. for example, lab b3 is in row b, column 3. figure 12. interconnect resources i/o element (ioe) row interconnect ioe ioe ioe ioe column interconnect lab b1 see figure 15 for details. see figure 14 for details. lab a3 lab b3 lab a1 lab a2 lab b2 ioe ioe cascade & carry chains to lab b4 to lab a4 to lab b5 to lab a5 ioe ioe ioe ioe ioe ioe ioe ioe ioe ioe ioe ioe ioe ioe
28 altera corporation flex 10k embedded programmable logic family data sheet i/o element an i/o element (ioe) contains a bidirectional i/o buffer and a register that can be used either as an input register for external data that requires a fast setup time, or as an output register for data that requires fast clock- to-output performance. in some cases, using an le register for an input register will result in a faster setup time than using an ioe register. ioes can be used as input, output, or bidirectional pins. the quartus and max+plus ii compilers use the programmable inversion option to invert signals from the row and column interconnect automatically where appropriate. figure 13 shows the ioe block diagram.
altera corporation 29 flex 10k embedded programmable logic family data sheet figure 13. bidirectional i/o registers note: (1) the output enable and input registers are le registers in the lab adjacent to the bidirectional pin. vcc oe[7..0] clk[1..0] ena[5..0] clrn[1..0] peripheral control bus clrn dq ena vcc 2 dedicated clock inputs slew-rate control open-drain output chip-wide output enable clk[3..2] 2 12 vcc vcc chip-wide reset 4 dedicated inputs row and column interconnect 4 vcc clrn dq ena chip-wide reset clrn dq ena chip-wide reset vcc input register (1) output register (1) oe register
30 altera corporation flex 10k embedded programmable logic family data sheet each ioe selects the clock, clear, clock enable, and output enable controls from a network of i/o control signals called the peripheral control bus. the peripheral control bus uses high-speed drivers to minimize signal skew across devices; it provides up to 12 peripheral control signals that can be allocated as follows: up to eight output enable signals up to six clock enable signals up to two clock signals up to two clear signals if more than six clock enable or eight output enable signals are required, each ioe on the device can be controlled by clock enable and output enable signals driven by specific les. in addition to the two clock signals available on the peripheral control bus, each ioe can use one of two dedicated clock pins. each peripheral control signal can be driven by any of the dedicated input pins or the first le of each lab in a particular row. in addition, an le in a different row can drive a column interconnect, which causes a row interconnect to drive the peripheral control signal. the chip-wide reset signal will reset all ioe registers, overriding any other control signals. tables 8 and 9 list the sources for each peripheral control signal, and the rows that can drive global signals. these tables also show how the output enable, clock enable, clock, and clear signals share 12 peripheral control signals.
altera corporation 31 flex 10k embedded programmable logic family data sheet table 8. epf10k10, epf10k20, epf10k30, epf10k40 & epf10k50 peripheral bus sources peripheral control signal epf10k10 epf10k10a epf10k20 epf10k30 epf10k30a epf10k40 epf10k50 epf10k50v oe0 row a row a row a row a row a oe1 row a row b row b row c row b oe2 row b row c row c row d row d oe3 row b row d row d row e row f oe4 row c row e row e row f row h oe5 row c row f row f row g row j clkena0/clk0/global0 row a row a row a row b row a clkena1/oe6/global1 row a row b row b row c row c clkena2/clr0 row b row c row c row d row e clkena3/oe7/global2 row b row d row d row e row g clkena4/clr1 row c row e row e row f row i clkena5/clk1/global3 row c row f row f row h row j table 9. epf10k70, epf10k100, epf10k130v & epf10k250a peripheral bus sources peripheral control signal epf10k70 epf10k100 epf10k100a epf10k130v epf10k250a oe0 row a row a row c row e oe1 row b row c row e row g oe2 row d row e row g row i oe3 row i row l row n row p oe4 row g row i row k row m oe5 row h row k row m row o clkena0/clk0/global0 row e row f row h row j clkena1/oe6/global1 row c row d row f row h clkena2/clr0 row b row b row d row f clkena3/oe7/global2 row f row h row j row l clkena4/clr1 row h row j row l row n clkena5/clk1/global3 row e row g row i row k
32 altera corporation flex 10k embedded programmable logic family data sheet signals on the peripheral control bus can also drive the four global signals, referred to as global0 through global3 in tables 8 and 9 . the internally generated signal can drive the global signal, providing the same low-skew, low-delay characteristics for an internally generated signal as for a signal driven by an input. this feature is ideal for internally generated clear or clock signals with high fan-out. when a global signal is driven by internal logic, the dedicated input pin that drives that global signal cannot be used. the dedicated input pin should be driven to a known logic state (such as ground) and not be allowed to float. when the chip-wide output enable pin is held low, it will tri-state all pins on the device. this option can be set in the global project device options menu. additionally, the registers in the ioe can be reset by holding the chip-wide reset pin low. row-to-ioe connections when an ioe is used as an input signal, it can drive two separate row channels. the signal is accessible by all les within that row. when an ioe is used as an output, the signal is driven by a multiplexer that selects a signal from the row channels. up to eight ioes connect to each side of each row channel. see figure 14 . figure 14. flex 10k row-to-ioe connections n n each ioe is driven by an m-to-1 multiplexer. each ioe can drive up to two row channels. ioe8 ioe1 m m row fasttrack interconnect n the values for m and n are provided in table 10 .
altera corporation 33 flex 10k embedded programmable logic family data sheet table 10 lists the flex 10k row-to-ioe interconnect resources. column-to-ioe connections when an ioe is used as an input, it can drive up to two separate column channels. when an ioe is used as an output, the signal is driven by a multiplexer that selects a signal from the column channels. two ioes connect to each side of the column channels. each ioe can be driven by column channels via a multiplexer. the set of column channels that each ioe can access is different for each ioe. see figure 15 . table 10. flex 10k row-to-ioe interconnect resources device channels per row ( n ) row channels per pin ( m ) epf10k10 epf10k10a 144 18 epf10k20 144 18 epf10k30 epf10k30a 216 27 epf10k40 216 27 epf10k50 epf10k50v 216 27 epf10k70 312 39 epf10k100 epf10k100a 312 39 epf10k130v 312 39 epf10k250a 456 57
34 altera corporation flex 10k embedded programmable logic family data sheet figure 15. flex 10k column-to-ioe connections table 11 lists the flex 10k column-to-ioe interconnect resources. each ioe is driven by an m-to-1 multiplexer. each ioe can drive up to two column channels. column interconnect n n m m n ioe1 ioe1 the values for m and n are provided in table 11 . table 11. flex 10k column-to-ioe interconnect resources device channels per column ( n ) column channel per pin ( m ) epf10k10 epf10k10a 24 16 epf10k20 24 16 epf10k30 epf10k30a 24 16 epf10k40 24 16 epf10k50 epf10k50v 24 16 epf10k70 24 16 epf10k100 epf10k100a 24 16 epf10k130v 32 24 epf10k250a 40 32
altera corporation 35 flex 10k embedded programmable logic family data sheet sameframe pin-outs flex 10ke devices support the sameframe pin-out feature for fineline bga packages. the sameframe pin-out feature is the arrangement of balls on fineline bga packages such that the lower-ball- count packages form a subset of the higher-ball-count packages. sameframe pin-outs provide the flexibility to migrate not only from device to device within the same package, but also from one package to another. a given printed circuit board (pcb) layout can support multiple device density/package combinations. for example, a single board layout can support a range of devices from an epf10k30e device in a 256-pin fineline bga package to an epf10k200s device in a 672-pin fineline bga package. the quartus and max+plus ii software provides support to design pcbs with sameframe pin-out devices. devices can be defined for present and future use. the max+plus ii software generates pin-outs describing how to lay out a board to take advantage of this migration (see figure 16 ). figure 16. sameframe pin-out example designed for 256-pinfineline bga package printed circuit board 100-pin fineline bga package (reduced i/o count or logic requirements) 256-pin fineline bga package (increased i/o count or logic requirements) 100-pin fineline bga 256-pin fineline bga
36 altera corporation flex 10k embedded programmable logic family data sheet clocklock & clockboost features to support high-speed designs, selected flex 10k devices offer optional clocklock and clockboost circuitry containing a phase-locked loop (pll) that is used to increase design speed and reduce resource usage. the clocklock circuitry uses a synchronizing pll that reduces the clock delay and skew within a device. this reduction minimizes clock-to-output and setup times while maintaining zero hold times. the clockboost circuitry, which provides a clock multiplier, allows the designer to enhance device area efficiency by sharing resources within the device. the clockboost feature allows the designer to distribute a low-speed clock and multiply that clock on-device. combined, the clocklock and clockboost features provide significant improvements in system performance and bandwidth. the clocklock and clockboost features in flex 10k devices are enabled through the max+plus ii software. external devices are not required to use these features. the output of the clocklock and clockboost circuits is not available at any of the device pins. the clocklock and clockboost circuitry locks onto the rising edge of the incoming clock. the circuit output can only drive the clock inputs of registers; the generated clock cannot be gated or inverted. the dedicated clock pin ( gclk1 ) supplies the clock to the clocklock and clockboost circuitry. when the dedicated clock pin is driving the clocklock or clockboost circuitry, it cannot drive elsewhere in the device. in designs that require both a multiplied and non-multiplied clock, the clock trace on the board can be connected to gclk1 . with the max+plus ii software, gclk1 can feed both the clocklock and clockboost circuitry in the flex 10k device. however, when both circuits are used, the other clock pin ( gclk0 ) cannot be used. figure 17 shows a block diagram of how to enable both the clocklock and clockboost circuits in the max+plus ii software. the example shown is a schematic, but a similar approach applies for designs created in ahdl, vhdl, and verilog hdl. when the clocklock and clockboost circuits are used simultaneously, the input frequency parameter must be the same for both circuits. in figure 17 , the input frequency must meet the requirements specified when the clockboost multiplication factor is two.
altera corporation 37 flex 10k embedded programmable logic family data sheet figure 17. enabling clocklock & clockboost in the same design to use both the clocklock and clockboost circuits in the same design, designers must use revision c epf10k100gc503-3dx devices and max+plus ii software versions 7.2 or higher. the die revision is indicated by the third digit of the nine-digit code on the top side of the device. f for more information on using the clocklock and clockboost features, see the clock management with clocklock & clockboost features white paper , which is available from altera literature services. output con?uration this section discusses the peripheral component interconnect (pci) pull-up clamping diode option, slew-rate control, open-drain output option, multivolt i/o interface, and power sequencing for flex 10k devices. the pci pull-up clamping diode, slew-rate control, and open-drain output options are controlled pin-by-pin via max+plus ii logic options. the multivolt i/o interface is controlled by connecting v ccio to a different voltage than v ccint . its effect can be simulated in the max+plus ii software via the global project device options dialog box (assign menu). pci clamping diodes the epf10k10a and epf10k30a devices have a pull-up clamping diode on every i/o, dedicated input, and dedicated clock pin. pci clamping diodes clamp the transient overshoot caused by reflected waves to the v ccio value and are required for 3.3-v pci compliance. clamping diodes can also be used to limit overshoot in other systems. dq dq a b aout bout gclk1 clklock clklock clockboost=1 input_frequency=50 clockboost=2 input_frequency=50
38 altera corporation flex 10k embedded programmable logic family data sheet clamping diodes are controlled on a pin-by-pin basis via a logic option in the max+plus ii software. when v ccio is 3.3 v, a pin that has the clamping diode turned on can be driven by a 2.5-v or 3.3-v signal, but not a 5.0-v signal. when v ccio is 2.5 v, a pin that has the clamping diode turned on can be driven by a 2.5-v signal, but not a 3.3-v or 5.0-v signal. however, a clamping diode can be turned on for a subset of pins, which allows devices to bridge between a 3.3-v pci bus and a 5.0-v device. slew-rate control the output buffer in each ioe has an adjustable output slew rate that can be configured for low-noise or high-speed performance. a slower slew rate reduces system noise and adds a maximum delay of approximately 2.9 ns. the fast slew rate should be used for speed-critical outputs in systems that are adequately protected against noise. designers can specify the slew rate on a pin-by-pin basis during design entry or assign a default slew rate to all pins on a device-wide basis. the slow slew rate setting affects only the falling edge of the output. open-drain output option flex 10k devices provide an optional open-drain (electrically equivalent to an open-collector) output for each i/o pin. this open-drain output enables the device to provide system-level control signals (e.g., interrupt and write enable signals) that can be asserted by any of several devices. it can also provide an additional wired- or plane. additionally, the max+plus ii software can convert tri-state buffers with grounded data inputs to open-drain pins automatically. open-drain output pins on flex 10k devices (with a pull-up resistor to the 5.0-v supply) can drive 5.0-v cmos input pins that require a v ih of 3.5 v. when the open-drain pin is active, it will drive low. when the pin is inactive, the trace will be pulled up to 5.0 v by the resistor. the open- drain pin will only drive low or tri-state; it will never drive high. the rise time is dependent on the value of the pull-up resistor and load impedance. the i ol current specification should be considered when selecting a pull-up resistor. output pins on 5.0-v flex 10k devices with v ccio = 3.3 v or 5.0 v (with a pull-up resistor to the 5.0-v supply) can also drive 5.0-v cmos input pins. in this case, the pull-up transistor will turn off when the pin voltage exceeds 3.3 v. therefore, the pin does not have to be open-drain.
altera corporation 39 flex 10k embedded programmable logic family data sheet multivolt i/o interface the flex 10k device architecture supports the multivolt i/o interface feature, which allows flex 10k devices to interface with systems of differing supply voltages. these devices have one set of v cc pins for internal operation and input buffers ( vccint ) and another set for i/o output drivers ( vccio ). table 12 describes the flex 10k device supply voltages and multivolt i/o support levels. note (1) the 240 pin qfp pagckages do not support the multivolt i/o feature so there are no v ccio pins. power sequencing & hot-socketing because flex 10k devices can be used in a multi-voltage environment, they have been designed specifically to tolerate any possible power-up sequence. the v ccio and v ccint power planes can be powered in any order. signals can be driven into flex 10ka devices before and during power up without damaging the device. additionally, flex 10ka devices do not drive out during power up. once operating conditions are reached, flex 10ka devices operate as specified by the user. ieee std. 1149.1 (jtag) boundary-scan support all flex 10k devices provide jtag bst circuitry that complies with the ieee std. 1149.1-1990 specification. all flex 10k devices can also be configured using the jtag pins through the bitblaster serial download cable, byteblaster parallel port download cable, or byteblastermv parallel port download cable, or via hardware that uses the jam tm programming and test language. jtag bst can be performed before or after configuration, but not during configuration. flex 10k devices support the jtag instructions shown in table 13 . table 12. supply voltages & multivolt i/o support levels devices supply voltage (v) multivolt i/o support levels (v) v ccint v ccio input output flex 10k (1) 5.0 5.0 3.3 or 5.0 5.0 5.0 3.3 3.3 or 5.0 3.3 or 5.0 epf10k50v (1) 3.3 3.3 3.3 or 5.0 3.3 or 5.0 epf10k130v 3.3 3.3 3.3 or 5.0 3.3 or 5.0 flex 10ka (1) 3.3 3.3 2.5, 3.3, or 5.0 3.3 or 5.0 3.3 2.5 2.5, 3.3, or 5.0 2.5
40 altera corporation flex 10k embedded programmable logic family data sheet the instruction register length of flex 10k devices is 10 bits. the usercode register length in flex 10k devices is 32 bits; 7 bits are determined by the user, and 25 bits are predetermined. tables 14 and 15 show the boundary-scan register length and device idcode information for flex 10k devices. table 13. flex 10k jtag instructions jtag instruction description sample/preload allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern output at the device pins. extest allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. bypass places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through a selected device to adjacent devices during normal device operation. usercode selects the user electronic signature (usercode) register and places it between the tdi and tdo pins, allowing the usercode to be serially shifted out of tdo . idcode selects the idcode register and places it between tdi and tdo , allowing the idcode to be serially shifted out of tdo . icr instructions these instructions are used when configuring a flex 10k device via jtag ports with a bitblaster, byteblaster, or byteblastermv download cable, or using a jam file ( .jam ) or jam byte-code file ( .jbc ) via an embedded processor. table 14. flex 10k boundary-scan register length device boundary-scan register length epf10k10, epf10k10a 480 epf10k20 624 epf10k30, epf10k30a 768 epf10k40 864 epf10k50, epf10k50v 960 epf10k70 1,104 epf10k100, epf10k100a 1,248 epf10k130v 1,440 epf10k250a 1,440
altera corporation 41 flex 10k embedded programmable logic family data sheet notes: (1) the most significant bit (msb) is on the left. (2) the least significant bit (lsb) for all jtag idcodes is 1 . flex 10k devices include weak pull-ups on jtag pins. f for more information, see the following documents: application note 39 (ieee 1149.1 (jtag) boundary-scan testing in altera devices) bitblaster serial download cable data sheet byteblaster parallel port download cable data sheet byteblastermv parallel port download cable data sheet jam programming & test language specification table 15. 32-bit flex 10k device idcode note (1) device idcode (32 bits) version (4 bits) part number (16 bits) manufacturer? identity (11 bits) 1 (1 bit) (2) epf10k10, epf10k10a 0000 0001 0000 0001 0000 00001101110 1 epf10k20 0000 0001 0000 0010 0000 00001101110 1 epf10k30, epf10k30a 0000 0001 0000 0011 0000 00001101110 1 epf10k40 0000 0001 0000 0100 0000 00001101110 1 epf10k50, epf10k50v 0000 0001 0000 0101 0000 00001101110 1 epf10k70 0000 0001 0000 0111 0000 00001101110 1 epf10k100, epf10k100a 0000 0000 0001 0000 0000 00001101110 1 epf10k130v 0000 0000 0001 0011 0000 00001101110 1 epf10k250a 0000 0000 0010 0101 0000 00001101110 1
42 altera corporation flex 10k embedded programmable logic family data sheet figure 18 shows the timing requirements for the jtag signals. figure 18. jtag waveforms table 16 shows the timing parameters and values for flex 10k devices. table 16. jtag timing parameters & values symbol parameter min max unit t jcp tck clock period 100 ns t jch tck clock high time 50 ns t jcl tck clock low time 50 ns t jpsu jtag port setup time 20 ns t jph jtag port hold time 45 ns t jpco jtag port clock to output 25 ns t jpzx jtag port high impedance to valid output 25 ns t jpxz jtag port valid output to high impedance 25 ns t jssu capture register setup time 20 ns t jsh capture register hold time 45 ns t jsco update register clock to output 35 ns t jszx update register high-impedance to valid output 35 ns t jsxz update register valid output to high impedance 35 ns tdo tck t jpzx t jpco t jph t jpxz t jcp t jpsu t jcl t jch tdi tms signal to be captured signal to be driven t jszx t jssu t jsh t jsco t jsxz
altera corporation 43 flex 10k embedded programmable logic family data sheet generic testing each flex 10k device is functionally tested. complete testing of each configurable sram bit and all logic functionality ensures 100 % yield. ac test measurements for flex 10k devices are made under conditions equivalent to those shown in figure 19 . multiple test patterns can be used to configure devices during all stages of the production flow. figure 19. flex 10k ac test conditions operating conditions tables 17 through 21 provide information on absolute maximum ratings, recommended operating conditions, dc operating conditions, and capacitance for 5.0-v flex 10k devices. vcc to test system c1 (includes jig capacitance) device input rise and fall times < 3 ns device output 250 ? (8.06 k ? ) [481 ?] 464 ? (703 ? ) [521 ? ] power supply transients can affect ac measurements. simultaneous transitions of multiple outputs should be avoided for accurate measurement. threshold tests must not be performed under ac conditions. large-amplitude, fast-ground-current transients normally occur as the device outputs discharge the load capacitances. when these transients ?w through the parasitic inductance between the device ground pin and the test system ground, signi?ant reductions in observable noise immunity can result. numbers without parentheses are for 5.0-v devices or outputs. numbers in parentheses are for 3.3-v devices or outputs. numbers in brackets are for 2.5-v devices or outputs. table 17. flex 10k 5.0-v device absolute maximum ratings note (1) symbol parameter conditions min max unit v cc supply voltage with respect to ground (2) 2.0 7.0 v v i dc input voltage 2.0 7.0 v i out dc output current, per pin 25 25 ma t stg storage temperature no bias 65 150 c t amb ambient temperature under bias 65 135 c t j junction temperature ceramic packages, under bias 150 c pqfp, tqfp, rqfp, and bga packages, under bias 135 c
44 altera corporation flex 10k embedded programmable logic family data sheet table 18. flex 10k 5.0-v device recommended operating conditions symbol parameter conditions min max unit v ccint supply voltage for internal logic and input buffers (3) , (4) 4.75 (4.50) 5.25 (5.50) v v ccio supply voltage for output buffers, 5.0-v operation (3) , (4) 4.75 (4.50) 5.25 (5.50) v supply voltage for output buffers, 3.3-v operation (3) , (4) 3.00 (3.00) 3.60 (3.60) v v i input voltage 0.5 v ccint + 0.5 v v o output voltage 0 v ccio v t a ambient temperature for commercial use 0 70 c for industrial use 40 85 c t j operating temperature for commercial use 0 85 c for industrial use 40 100 c t r input rise time 40 ns t f input fall time 40 ns table 19. flex 10k 5.0-v device dc operating conditions notes (5) , (6) symbol parameter conditions min typ max unit v ih high-level input voltage 2.0 v ccint + 0.5 v v il low-level input voltage 0.5 0.8 v v oh 5.0-v high-level ttl output voltage i oh = 4 ma dc, v ccio = 4.75 v (7) 2.4 v 3.3-v high-level ttl output voltage i oh = 4 ma dc, v ccio = 3.00 v (7) 2.4 v 3.3-v high-level cmos output voltage i oh = 0.1 ma dc, v ccio = 3.00 v (7) v ccio 0.2 v v ol 5.0-v low-level ttl output voltage i ol = 12 ma dc, v ccio = 4.75 v (8) 0.45 v 3.3-v low-level ttl output voltage i ol = 12 ma dc, v ccio = 3.00 v (8) 0.45 v 3.3-v low-level cmos output voltage i ol = 0.1 ma dc, v ccio = 3.00 v (8) 0.2 v i i input pin leakage current v i = v cc or ground 10 10 a i oz tri-stated i/o pin leakage current v o = v cc or ground 40 40 a i cc0 v cc supply current (standby) v i = ground, no load 0.5 10 ma
altera corporation 45 flex 10k embedded programmable logic family data sheet notes to tables: (1) see the operating requirements for altera devices data sheet . (2) minimum dc input voltage is ?.5 v. during transitions, the inputs may undershoot to ?.0 v for input currents less than 100 ma and periods shorter than 20 ns. (3) numbers in parentheses are for industrial-temperature-range devices. (4) maximum v cc rise time is 100 ms. v cc must rise monotonically. (5) typical values are for t a = 25 c and v cc = 5.0 v. (6) these values are specified under table 18 on page 44 . (7) the i oh parameter refers to high-level ttl or cmos output current. (8) the i ol parameter refers to low-level ttl or cmos output current. this parameter applies to open-drain pins as well as output pins. (9) capacitance is sample-tested only. table 20. 5.0-v device capacitance of epf10k10, epf10k20 & epf10k30 devices note (9) symbol parameter conditions min max unit c in input capacitance v in = 0 v, f = 1.0 mhz 8 pf c inclk input capacitance on dedicated clock pin v in = 0 v, f = 1.0 mhz 12 pf c out output capacitance v out = 0 v, f = 1.0 mhz 8 pf table 21. 5.0-v device capacitance of epf10k40, epf10k50, epf10k70 & epf10k100 devices note (9) symbol parameter conditions min max unit c in input capacitance v in = 0 v, f = 1.0 mhz 10 pf c inclk input capacitance on dedicated clock pin v in = 0 v, f = 1.0 mhz 15 pf c out output capacitance v out = 0 v, f = 1.0 mhz 10 pf
46 altera corporation flex 10k embedded programmable logic family data sheet figure 20 shows the typical output drive characteristics of flex 10k devices with 5.0-v and 3.3-v v ccio . the output driver is compliant with the 5.0-v pci local bus specification, revision 2.2 (for 5.0-v v ccio ). figure 20. output drive characteristics of flex 10k devices tables 22 through 25 provide information on absolute maximum ratings, recommended operating conditions, dc operating conditions, and capacitance for epf10k50v and epf10k130v devices. v o output voltage (v) 12345 30 60 90 150 120 i ol i oh 45 3.3 v ccint = 5.0 v v ccio = 3.3 v room temperature v o output voltage (v) 12345 30 60 90 150 120 i ol i oh v ccint = 5.0 v v ccio = 5.0 v room temp erature typical i o output current (ma) typical i o output current (ma) 5.0-v 3.3-v table 22. epf10k50v & epf10k130v device absolute maximum ratings note (1) symbol parameter conditions min max unit v cc supply voltage with respect to ground (2) 0.5 4.6 v v i dc input voltage 2.0 5.75 v i out dc output current, per pin 25 25 ma t stg storage temperature no bias 65 150 c t amb ambient temperature under bias 65 135 c t j junction temperature ceramic packages, under bias 150 c rqfp and bga packages, under bias 135 c
altera corporation 47 flex 10k embedded programmable logic family data sheet table 23. epf10k50v & epf10k130v device recommended operating conditions symbol parameter conditions min max unit v ccint supply voltage for internal logic and input buffers (3) , (4) 3.00 (3.00) 3.60 (3.60) v v ccio supply voltage for output buffers (3) , (4) 3.00 (3.00) 3.60 (3.60) v v i input voltage (5) -0.5 5.75 v v o output voltage 0 v ccio v t a ambient temperature for commercial use 0 70 c for industrial use 40 85 c t j operating temperature for commercial use 0 85 c for industrial use 40 100 c t r input rise time 40 ns t f input fall time 40 ns table 24. epf10k50v & epf10k130v device dc operating conditions notes (6) , (7) symbol parameter conditions min typ max unit v ih high-level input voltage 2.0 5.75 v v il low-level input voltage 0.5 0.8 v v oh 3.3-v high-level ttl output voltage i oh = 8 ma dc (8) 2.4 v 3.3-v high-level cmos output voltage i oh = 0.1 ma dc (8) v ccio 0.2 v v ol 3.3-v low-level ttl output voltage i ol = 8 ma dc (9) 0.45 v 3.3-v low-level cmos output voltage i ol = 0.1 ma dc (9) 0.2 v i i input pin leakage current v i = 5.3 v to 0.3 v 10 10 a i oz tri-stated i/o pin leakage current v o = 5.3 v to 0.3 v 10 10 a i cc0 v cc supply current (standby) v i = ground, no load 0.3 10 ma v i = ground, no load (10) 10 ma
48 altera corporation flex 10k embedded programmable logic family data sheet notes to tables: (1) see the operating requirements for altera devices data sheet . (2) minimum dc input voltage is ?.5 v. during transitions, the inputs may undershoot to ?.0 v or overshoot to 5.75 v for input currents less than 100 ma and periods shorter than 20 ns. (3) numbers in parentheses are for industrial-temperature-range devices. (4) maximum v cc rise time is 100 ms. v cc must rise monotonically. (5) epf10k50v and epf10k130v device inputs may be driven before v ccint and v ccio are powered. (6) typical values are for t a = 25 c and v cc = 3.3 v. (7) these values are specified under the epf10k50v and epf10k130v device recommended operating conditions in table 23 on page 47 . (8) the i oh parameter refers to high-level ttl or cmos output current. (9) the i ol parameter refers to low-level ttl or cmos output current. this parameter applies to open-drain pins as well as output pins. (10) this parameter applies to -1 speed grade epf10k50v devices, -2 speed grade epf10k50v industrial temperature devices, and -2 speed grade epf10k130v devices. (11) capacitance is sample-tested only. figure 21 shows the typical output drive characteristics of epf10k50v and epf10k130v devices. figure 21. output drive characteristics of epf10k50v & epf10k130v devices table 25. epf10k50v & epf10k130v device capacitance note (11) symbol parameter conditions min max unit c in input capacitance v in = 0 v, f = 1.0 mhz 10 pf c inclk input capacitance on dedicated clock pin v in = 0 v, f = 1.0 mhz 15 pf c out output capacitance v out = 0 v, f = 1.0 mhz 10 pf v o output voltage (v) 123 20 40 60 i oh v cc = 3.3 v room temperature i ol typical i o output current (ma)
altera corporation 49 flex 10k embedded programmable logic family data sheet tables 26 through 31 provide information on absolute maximum ratings, recommended operating conditions, dc operating conditions, and capacitance for 3.3-v flex 10k devices. table 26. flex 10ka 3.3-v device absolute maximum ratings note (1) symbol parameter conditions min max unit v cc supply voltage with respect to ground (2) 0.5 4.6 v v i dc input voltage 2.0 5.75 v i out dc output current, per pin 25 25 ma t stg storage temperature no bias 65 150 c t amb ambient temperature under bias 65 135 c t j junction temperature ceramic packages, under bias 150 c pqfp, tqfp, rqfp, and bga packages, under bias 135 c table 27. flex 10ka 3.3-v device recommended operating conditions symbol parameter conditions min max unit v ccint supply voltage for internal logic and input buffers (3) , (4) 3.00 (3.00) 3.60 (3.60) v v ccio supply voltage for output buffers, 3.3-v operation (3) , (4) 3.00 (3.00) 3.60 (3.60) v supply voltage for output buffers, 2.5-v operation (3) , (4) 2.30 (2.30) 2.70 (2.70) v v i input voltage (5) 0.5 5.75 v v o output voltage 0 v ccio v t a ambient temperature for commercial use 0 70 c for industrial use 40 85 c t j operating temperature for commercial use 0 85 c for industrial use 40 100 c t r input rise time 40 ns t f input fall time 40 ns
50 altera corporation flex 10k embedded programmable logic family data sheet table 28. flex 10ka 3.3-v device dc operating conditions notes (6) , (7) symbol parameter conditions min typ max unit v ih high-level input voltage 1.7 or 0.5 v ccint , whichever is lower 5.75 v v il low-level input voltage 0.5 0.3 v ccint v v oh 3.3-v high-level ttl output voltage i oh = 11 ma dc, v ccio = 3.00 v (8) 2.4 v 3.3-v high-level cmos output voltage i oh = 0.1 ma dc, v ccio = 3.00 v (8) v ccio 0.2 v 3.3-v high-level pci output voltage i oh = 0.5 ma dc, v ccio = 3.00 to 3.60 v (8) 0.9 v ccio v 2.5-v high-level output voltage i oh = 0.1 ma dc, v ccio = 2.30 v (8) 2.1 v i oh = 1 ma dc, v ccio = 2.30 v (8) 2.0 v i oh = 2 ma dc, v ccio = 2.30 v (8) 1.7 v v ol 3.3-v low-level ttl output voltage i ol = 9 ma dc, v ccio = 3.00 v (9) 0.45 v 3.3-v low-level cmos output voltage i ol = 0.1 ma dc, v ccio = 3.00 v (9) 0.2 v 3.3-v low-level pci output voltage i ol = 1.5 ma dc, v ccio = 3.00 to 3.60 v (9) 0.1 v ccio v 2.5-v low-level output voltage i ol = 0.1 ma dc, v ccio = 2.30 v (9) 0.2 v i ol = 1 ma dc, v ccio = 2.30 v (9) 0.4 v i ol = 2 ma dc, v ccio = 2.30 v (9) 0.7 v i i input pin leakage current v i = 5.3 v to 0.3 v 10 10 a i oz tri-stated i/o pin leakage current v o = 5.3 v to 0.3 v 10 10 a i cc0 v cc supply current (standby) v i = ground, no load 0.3 10 ma v i = ground, no load (10) 10 ma
altera corporation 51 flex 10k embedded programmable logic family data sheet notes to tables: (1) see the operating requirements for altera devices data sheet . (2) minimum dc voltage input is ?.5 v. during transitions, the inputs may undershoot to ?.0 v or overshoot to 5.75 v for input currents less than 100 ma and periods shorter than 20 ns. flex 10ka devices can withstand a 11 v pulse for 11ns. (3) numbers in parentheses are for industrial-temperature-range devices. (4) maximum v cc rise time is 100 ms, and v cc must rise monotonically. (5) flex 10ka device inputs may be driven before v ccint and v ccio are powered. (6) typical values are for t a = 25 c and v cc = 3.3 v. (7) these values are specified under table 27 on page 49 . (8) the i oh parameter refers to high-level ttl, pci, or cmos output current. (9) the i ol parameter refers to low-level ttl, pci, or cmos output current. this parameter applies to open-drain pins as well as output pins. (10) this parameter applies to all -1 speed grade commercial temperature devices and all -2 speed grade industrial-temperature devices. (11) capacitance is sample-tested only. table 29. 3.3-v device capacitance of epf10k10a & epf10k30a devices note (11) symbol parameter conditions min max unit c in input capacitance v in = 0 v, f = 1.0 mhz 8 pf c inclk input capacitance on dedicated clock pin v in = 0 v, f = 1.0 mhz 12 pf c out output capacitance v out = 0 v, f = 1.0 mhz 8 pf table 30. 3.3-v device capacitance of epf10k100a devices note (11) symbol parameter conditions min max unit c in input capacitance v in = 0 v, f = 1.0 mhz 10 pf c inclk input capacitance on dedicated clock pin v in = 0 v, f = 1.0 mhz 15 pf c out output capacitance v out = 0 v, f = 1.0 mhz 10 pf table 31. 3.3-v device capacitance of epf10k250a devices note (11) symbol parameter conditions min max unit c in input capacitance v in = 0 v, f = 1.0 mhz 10 pf c inclk input capacitance on dedicated clock pin v in = 0 v, f = 1.0 mhz 15 pf c out output capacitance v out = 0 v, f = 1.0 mhz 10 pf
52 altera corporation flex 10k embedded programmable logic family data sheet figure 22 shows the typical output drive characteristics of epf10k10a, epf10k30a, epf10k100a, and epf10k250a devices with 3.3-v and 2.5-v v ccio . the output driver is compliant with the 3.3-v pci local bus specification , revision 2.2 (with 3.3-v v ccio ). moreover, device analysis shows that the epf10k10a, epf10k30a, and epf 10k100a devices can drive a 5.0-v pci bus with eight or fewer loads. figure 22. output drive characteristics for epf10k10a, epf10k30a & epf10k100a devices figure 23 shows the typical output drive characteristics of the epf10k250a device with 3.3-v and 2.5-v v ccio . v o output voltage (v) 1234 i oh v o output voltage (v) 1234 10 20 30 50 60 40 10 20 30 50 60 40 i ol i oh v v v ccint = 3.3 v ccio = 3.3 room temperature v ccint = 3.3 v v ccio = 2.5 v room temperature i ol typical i o output current (ma) typical i o output current (ma)
altera corporation 53 flex 10k embedded programmable logic family data sheet figure 23. output drive characteristics for epf10k250a device timing model the continuous, high-performance fasttrack interconnect routing resources ensure predictable performance and accurate simulation and timing analysis. this predictable performance contrasts with that of fpgas, which use a segmented connection scheme and therefore have unpredictable performance. device performance can be estimated by following the signal path from a source, through the interconnect, to the destination. for example, the registered performance between two les on the same row can be calculated by adding the following parameters: le register clock-to-output delay ( t co ) interconnect delay ( t samerow ) le look-up table delay ( t lut ) le register setup time ( t su ) the routing delay depends on the placement of the source and destination les. a more complex registered path may involve multiple combinatorial les between the source and destination les. v cci nt = 3.3 v v cci o = 3.3 v room temperature v cci nt = 3.3 v v cci o = 2.5 v room temperature v o output voltage (v) 1234 v o output voltage (v) 1234 10 20 30 50 40 10 20 30 50 40 i ol i oh i ol i oh typical i o output current (ma) typical i o output current (ma)
54 altera corporation flex 10k embedded programmable logic family data sheet timing simulation and delay prediction are available with the max+plus ii simulator and timing analyzer, or with industry- standard eda tools. the simulator offers both pre-synthesis functional simulation to evaluate logic design accuracy and post-synthesis timing simulation with 0.1-ns resolution. the timing analyzer provides point- to-point timing delay information, setup and hold time analysis, and device-wide performance analysis. figure 24 shows the overall timing model, which maps the possible paths to and from the various elements of the flex 10k device. figure 24. flex 10k device timing model dedicated clock/input interconnect i/o element logic element embedded array block
altera corporation 55 flex 10k embedded programmable logic family data sheet figures 25 through 27 show the delays that correspond to various paths and functions within the le, ioe, and eab timing models. figure 25. flex 10k device le timing model t cgenr t co t comb t su t h t pre t clr register delays lut delay t lut t rlut t clut carry chain delay carry-in cascade-in data-out t cgen t cico packed register delay t packed register control delay t c t en data-in control-in t casc cascade-out carry-out t labcarry t labcasc
56 altera corporation flex 10k embedded programmable logic family data sheet figure 26. flex 10k device ioe timing model figure 27. flex 10k device eab timing model figures 28 shows the timing model for bidirectional i/o pin timing. data-in i/o register delays t ioco t iocomb t iosu t ioh t ioclr output data delay t iod i/o element control delay t ioc input register delay t inreg output delays t od1 t od2 t od3 t xz t zx1 t zx2 t zx3 i/o register feedback delay t iofd input delay t incomb clock enable clear data feedback into fasttrack interconnect clock output enable eab data input delays t eabdata1 t eabdata2 data-in write enable input delays t eabwe1 t eabwe2 eab clock delay t eabclk input register delays t eabco t eabbypass t eabsu t eabh t eabch t eabcl ram/rom block delays t aa t dd t wp t wdsu t wdh t wasu t wah t wo output register delays t eabco t eabbypass t eabsu t eabh t eabch t eabcl t eabout address we input register clock output register clock data-out eab output delay
altera corporation 57 flex 10k embedded programmable logic family data sheet figure 28. synchronous bidirectional pin external timing model note: (1) the output enable and input registers are le registers in the lab adjacent to the bidirectional pin. tables 32 through 36 describe the flex 10k device internal timing parameters. these internal timing parameters are expressed as worst-case values. using hand calculations, these parameters can be used to estimate design performance. however, before committing designs to silicon, actual worst-case performance should be modeled using timing simulation and analysis. tables 37 through 39 describe flex 10k external timing parameters. prn clrn dq prn clrn dq prn clrn dq dedicated clock (1) (1) bidirectional pin ioe register table 32. le timing microparameters (part 1 of 2) note (1) symbol parameter conditions t lut lut delay for data-in t clut lut delay for carry-in t rlut lut delay for le register feedback t packed data-in to packed register delay t en le register enable delay t cico carry-in to carry-out delay t cgen data-in to carry-out delay t cgenr le register feedback to carry-out delay t casc cascade-in to cascade-out delay t c le register control signal delay
58 altera corporation flex 10k embedded programmable logic family data sheet t co le register clock-to-output delay t comb combinatorial delay t su le register setup time for data and enable signals before clock; le register recovery time after asynchronous clear, preset, or load t h le register hold time for data and enable signals after clock t pre le register preset delay t clr le register clear delay t ch minimum clock high time from clock pin t cl minimum clock low time from clock pin table 33. ioe timing microparameters note (1) symbol parameter conditions t iod ioe data delay t ioc ioe register control signal delay t ioco ioe register clock-to-output delay t iocomb ioe combinatorial delay t iosu ioe register setup time for data and enable signals before clock; ioe register recovery time after asynchronous clear t ioh ioe register hold time for data and enable signals after clock t ioclr ioe register clear time t od1 output buffer and pad delay, slow slew rate = off, v ccio = v ccint c1 = 35 pf (2) t od2 output buffer and pad delay, slow slew rate = off, v ccio = low voltage c1 = 35 pf (3) t od3 output buffer and pad delay, slow slew rate = on c1 = 35 pf (4) t xz ioe output buffer disable delay t zx1 ioe output buffer enable delay, slow slew rate = off, v ccio = v ccint c1 = 35 pf (2) t zx2 ioe output buffer enable delay, slow slew rate = off, v ccio = low voltage c1 = 35 pf (3) t zx3 ioe output buffer enable delay, slow slew rate = on c1 = 35 pf (4) t inreg ioe input pad and buffer to ioe register delay t iofd ioe register feedback delay t incomb ioe input pad and buffer to fasttrack interconnect delay table 32. le timing microparameters (part 2 of 2) note (1) symbol parameter conditions
altera corporation 59 flex 10k embedded programmable logic family data sheet table 34. eab timing microparameters note (1) symbol parameter conditions t eabdata1 data or address delay to eab for combinatorial input t eabdata2 data or address delay to eab for registered input t eabwe1 write enable delay to eab for combinatorial input t eabwe2 write enable delay to eab for registered input t eabclk eab register clock delay t eabco eab register clock-to-output delay t eabbypass bypass register delay t eabsu eab register setup time before clock t eabh eab register hold time after clock t eabch clock high time t eabcl clock low time t aa address access delay t wp write pulse width t wdsu data setup time before falling edge of write pulse (5) t wdh data hold time after falling edge of write pulse (5) t wasu address setup time before rising edge of write pulse (5) t wah address hold time after falling edge of write pulse (5) t wo write enable to data output valid delay t dd data-in to data-out valid delay t eabout data-out delay
60 altera corporation flex 10k embedded programmable logic family data sheet table 35. eab timing macroparameters notes (1) , (6) symbol parameter conditions t eabaa eab address access delay t eabrccomb eab asynchronous read cycle time t eabrcreg eab synchronous read cycle time t eabwp eab write pulse width t eabwccomb eab asynchronous write cycle time t eabwcreg eab synchronous write cycle time t eabdd eab data-in to data-out valid delay t eabdataco eab clock-to-output delay when using output registers t eabdatasu eab data/address setup time before clock when using input register t eabdatah eab data/address hold time after clock when using input register t eabwesu eab we setup time before clock when using input register t eabwesh eab we hold time after clock when using input register t eabwdsu eab data setup time before falling edge of write pulse when not using input registers t eabwdh eab data hold time after falling edge of write pulse when not using input registers t eabwasu eab address setup time before rising edge of write pulse when not using input registers t eabwah eab address hold time after falling edge of write pulse when not using input registers t eabwo eab write enable to data output valid delay
altera corporation 61 flex 10k embedded programmable logic family data sheet table 36. interconnect timing microparameters note (1) symbol parameter conditions t samelab routing delay for an le driving another le in the same lab t samerow routing delay for a row ioe, le, or eab driving a row ioe, le, or eab in the same row (7) t samecolumn routing delay for an le driving an ioe in the same column (7) t diffrow routing delay for a column ioe, le, or eab driving an le or eab in a different row (7) t tworows routing delay for a row ioe or eab driving an le or eab in a different row (7) t leperiph routing delay for an le driving a control signal of an ioe via the peripheral control bus (7) t labcarry routing delay for the carry-out signal of an le driving the carry-in signal of a different le in a different lab t labcasc routing delay for the cascade-out signal of an le driving the cascade-in signal of a different le in a different lab t din2ioe delay from dedicated input pin to ioe control input (7) t din2le delay from dedicated input pin to le or eab control input (7) t dclk2ioe delay from dedicated clock pin to ioe clock (7) t dclk2le delay from dedicated clock pin to le or eab clock (7) t din2data delay from dedicated input or clock to le or eab data (7) table 37. external reference timing parameters note (8) symbol parameter conditions t drr register-to-register delay via four les, three row interconnects, and four local interconnects (9) table 38. external timing parameters note (10) symbol parameter conditions t insu setup time with global clock at ioe register t inh hold time with global clock at ioe register t outco clock-to-output delay with global clock at ioe register
62 altera corporation flex 10k embedded programmable logic family data sheet notes to tables: (1) microparameters are timing delays contributed by individual architectural elements. these parameters cannot be measured explicitly. (2) operating conditions: v ccio = 5.0 v 5 % for commercial use in flex 10k devices. v ccio = 5.0 v 10 % for industrial use in flex 10k devices. v ccio = 3.3 v 10 % for commercial or industrial use in flex 10ka devices. (3) operating conditions: v ccio = 3.3 v 10 % for commercial or industrial use in flex 10k devices. v ccio = 2.5 v 0.2 v for commercial or industrial use in flex 10ka devices. (4) operating conditions: v ccio = 2.5 v, 3.3 v, or 5.0 v. (5) because the ram in the eab is self-timed, this parameter can be ignored when the we signal is registered. (6) eab macroparameters are internal parameters that can simplify predicting the behavior of an eab at its boundary; these parameters are calculated by summing selected microparameters. (7) these parameters are worst-case values for typical applications. post-compilation timing simulation and timing analysis are required to determine actual worst-case performance. (8) external reference timing parameters are factory-tested, worst-case values specified by altera. a representative subset of signal paths is tested to approximate typical device applications. (9) contact altera applications for test circuit specifications and test conditions. (10) these timing parameters are sample-tested only. table 39. external bidirectional timing parameters note (10) symbol parameter condition t insubidir setup time for bidirectional pins with global clock at adjacent le register t inhbidir hold time for bidirectional pins with global clock at adjacent le register t outcobidir clock-to-output delay for bidirectional pins with global clock at ioe register t xzbidir synchronous ioe output buffer disable delay t zxbidir synchronous ioe output buffer enable delay, slow slew rate = off
altera corporation 63 flex 10k embedded programmable logic family data sheet figures 29 and 30 show the asynchronous and synchronous timing waveforms, respectively, for the eab macroparameters in table 34 . figure 29. eab asynchronous timing waveforms eab asynchronous write eab asynchronous read we a0 d0 d3 t eabrccomb a1 a2 a3 d2 t eabaa d1 address data-out we a0 din1 dout2 t eabdd a1 a2 din1 din0 t eabwccomb t eabwasu t eabwah t eabwdh t eabwdsu t eabwp din0 data-in address data-out
64 altera corporation flex 10k embedded programmable logic family data sheet figure 30. eab synchronous timing waveforms we clk eab synchronous read a0 d2 t eabdatasu t eabrcreg t eabdataco a1 a2 a3 d1 t eabdatah a0 we clk dout0 din1 din2 din3 din2 t eabwesu t eabwcreg t eabweh t eabdataco a1 a2 a3 a2 din3 din2 din1 t eabdatah t eabdatasu eab synchronous write (eab output registers used) dout1 address data-out address data-out data-in
altera corporation 65 flex 10k embedded programmable logic family data sheet tables 40 through 48 show epf10k10 and epf10k20 device internal and external timing parameters. table 40. epf10k10 & epf10k20 device le timing microparameters note (1) symbol speed grade unit -3 -4 min max min max t lut 1.4 1.7 ns t clut 0.6 0.7 ns t rlut 1.5 1.9 ns t packed 0.6 0.9 ns t en 1.0 1.2 ns t cico 0.2 0.3 ns t cgen 0.9 1.2 ns t cgenr 0.9 1.2 ns t casc 0.8 0.9 ns t c 1.3 1.5 ns t co 0.9 1.1 ns t comb 0.5 0.6 ns t su 1.3 2.5 ns t h 1.4 1.6 ns t pre 1.0 1.2 ns t clr 1.0 1.2 ns t ch 4.0 4.0 ns t cl 4.0 4.0 ns
66 altera corporation flex 10k embedded programmable logic family data sheet table 41. epf10k10 & epf10k20 device ioe timing microparameters note (1) symbol speed grade unit -3 -4 min max min max t iod 1.3 1.6 ns t ioc 0.5 0.7 ns t ioco 0.2 0.2 ns t iocomb 0.0 0.0 ns t iosu 2.8 3.2 ns t ioh 1.0 1.2 ns t ioclr 1.0 1.2 ns t od1 2.6 3.5 ns t od2 4.9 6.4 ns t od3 6.3 8.2 ns t xz 4.5 5.4 ns t zx1 4.5 5.4 ns t zx2 6.8 8.3 ns t zx3 8.2 10.1 ns t inreg 6.0 7.5 ns t iofd 3.1 3.5 ns t incomb 3.1 3.5 ns
altera corporation 67 flex 10k embedded programmable logic family data sheet table 42. epf10k10 & epf10k20 device eab internal microparameters note (1) symbol speed grade unit -3 -4 min max min max t eabdata1 1.5 1.9 ns t eabdata2 4.8 6.0 ns t eabwe1 1.0 1.2 ns t eabwe2 5.0 6.2 ns t eabclk 1.0 2.2 ns t eabco 0.5 0.6 ns t eabbypass 1.5 1.9 ns t eabsu 1.5 1.8 ns t eabh 2.0 2.5 ns t aa 8.7 10.7 ns t wp 5.8 7.2 ns t wdsu 1.6 2.0 ns t wdh 0.3 0.4 ns t wasu 0.5 0.6 ns t wah 1.0 1.2 ns t wo 5.0 6.2 ns t dd 5.0 6.2 ns t eabout 0.5 0.6 ns t eabch 4.0 4.0 ns t eabcl 5.8 7.2 ns
68 altera corporation flex 10k embedded programmable logic family data sheet table 43. epf10k10 & epf10k20 device eab internal timing macroparameters note (1) symbol speed grade unit -3 -4 min max min max t eabaa 13.7 17.0 ns t eabrccomb 13.7 17.0 ns t eabrcreg 9.7 11.9 ns t eabwp 5.8 7.2 ns t eabwccomb 7.3 9.0 ns t eabwcreg 13.0 16.0 ns t eabdd 10.0 12.5 ns t eabdataco 2.0 3.4 ns t eabdatasu 5.3 5.6 ns t eabdatah 0.0 0.0 ns t eabwesu 5.5 5.8 ns t eabweh 0.0 0.0 ns t eabwdsu 5.5 5.8 ns t eabwdh 0.0 0.0 ns t eabwasu 2.1 2.7 ns t eabwah 0.0 0.0 ns t eabwo 9.5 11.8 ns
altera corporation 69 flex 10k embedded programmable logic family data sheet table 44. epf10k10 device interconnect timing microparameters note (1) symbol speed grade unit -3 -4 min max min max t din2ioe 4.8 6.2 ns t din2le 2.6 3.8 ns t din2data 4.3 5.2 ns t dclk2ioe 3.4 4.0 ns t dclk2le 2.6 3.8 ns t samelab 0.6 0.6 ns t samerow 3.6 3.8 ns t samecolumn 0.9 1.1 ns t diffrow 4.5 4.9 ns t tworows 8.1 8.7 ns t leperiph 3.3 3.9 ns t labcarry 0.5 0.8 ns t labcasc 2.7 3.0 ns table 45. epf10k20 device interconnect timing microparameters note (1) symbol speed grade unit -3 -4 min max min max t din2ioe 5.2 6.6 ns t din2le 2.6 3.8 ns t din2data 4.3 5.2 ns t dclk2ioe 4.3 4.0 ns t dclk2le 2.6 3.8 ns t samelab 0.6 0.6 ns t samerow 3.7 3.9 ns t samecolumn 1.4 1.6 ns t diffrow 5.1 5.5 ns t tworows 8.8 9.4 ns t leperiph 4.7 5.6 ns t labcarry 0.5 0.8 ns t labcasc 2.7 3.0 ns
70 altera corporation flex 10k embedded programmable logic family data sheet notes to tables: (1) all timing parameters are described in tables 32 through 39 in this data sheet. (2) using an le to register the signal may provide a lower setup time. (3) this parameter is specified by characterization. table 46. epf10k10 & epf10k20 device external timing parameters note (1) symbol speed grade unit -3 -4 min max min max t drr 16.1 20.0 ns t insu (2) , (3) 5.5 6.0 ns t inh (3) 0.0 0.0 ns t outco (3) 2.0 6.7 2.0 8.4 ns table 47. epf10k10 device external bidirectional timing parameters note (1) symbol speed grade unit -3 -4 min max min max t insubidir 4.5 5.6 ns t inhbidir 0.0 0.0 ns t outcobidir 2.0 6.7 2.0 8.4 ns t xzbidir 10.5 13.4 ns t zxbidir 10.5 13.4 ns table 48. epf10k20 device external bidirectional timing parameters note (1) symbol speed grade unit -3 -4 min max min max t insubidir 4.6 5.7 ns t inhbidir 0.0 0.0 ns t outcobidir 2.0 6.7 2.0 8.4 ns t xzbidir 10.5 13.4 ns t zxbidir 10.5 13.4 ns
altera corporation 71 flex 10k embedded programmable logic family data sheet tables 49 through 57 show epf10k30, epf10k40, and epf10k50 device internal and external timing parameters. table 49. epf10k30, epf10k40 & epf10k50 device le timing microparameters note (1) symbol speed grade unit -3 -4 min max min max t lut 1.3 1.8 ns t clut 0.6 0.6 ns t rlut 1.5 2.0 ns t packed 0.5 0.8 ns t en 0.9 1.5 ns t cico 0.2 0.4 ns t cgen 0.9 1.4 ns t cgenr 0.9 1.4 ns t casc 1.0 1.2 ns t c 1.3 1.6 ns t co 0.9 1.2 ns t comb 0.6 0.6 ns t su 1.4 1.4 ns t h 0.9 1.3 ns t pre 0.9 1.2 ns t clr 0.9 1.2 ns t ch 4.0 4.0 ns t cl 4.0 4.0 ns
72 altera corporation flex 10k embedded programmable logic family data sheet table 50. epf10k30, epf10k40 & epf10k50 device ioe timing microparameters note (1) symbol speed grade unit -3 -4 min max min max t iod 0.4 0.6 ns t ioc 0.5 0.9 ns t ioco 0.4 0.5 ns t iocomb 0.0 0.0 ns t iosu 3.1 3.5 ns t ioh 1.0 1.9 ns t ioclr 1.0 1.2 ns t od1 3.3 3.6 ns t od2 5.6 6.5 ns t od3 7.0 8.3 ns t xz 5.2 5.5 ns t zx1 5.2 5.5 ns t zx2 7.5 8.4 ns t zx3 8.9 10.2 ns t inreg 7.7 10.0 ns t iofd 3.3 4.0 ns t incomb 3.3 4.0 ns
altera corporation 73 flex 10k embedded programmable logic family data sheet table 51. epf10k30, epf10k40 & epf10k50 device eab internal microparameters note (1) symbol speed grade unit -3 -4 min max min max t eabdata1 1.5 1.9 ns t eabdata2 4.8 6.0 ns t eabwe1 1.0 1.2 ns t eabwe2 5.0 6.2 ns t eabclk 1.0 2.2 ns t eabco 0.5 0.6 ns t eabbypass 1.5 1.9 ns t eabsu 1.5 1.8 ns t eabh 2.0 2.5 ns t aa 8.7 10.7 ns t wp 5.8 7.2 ns t wdsu 1.6 2.0 ns t wdh 0.3 0.4 ns t wasu 0.5 0.6 ns t wah 1.0 1.2 ns t wo 5.0 6.2 ns t dd 5.0 6.2 ns t eabout 0.5 0.6 ns t eabch 4.0 4.0 ns t eabcl 5.8 7.2 ns
74 altera corporation flex 10k embedded programmable logic family data sheet table 52. epf10k30, epf10k40 & epf10k50 device eab internal timing macroparameters note (1) symbol speed grade unit -3 -4 min max min max t eabaa 13.7 17.0 ns t eabrccomb 13.7 17.0 ns t eabrcreg 9.7 11.9 ns t eabwp 5.8 7.2 ns t eabwccomb 7.3 9.0 ns t eabwcreg 13.0 16.0 ns t eabdd 10.0 12.5 ns t eabdataco 2.0 3.4 ns t eabdatasu 5.3 5.6 ns t eabdatah 0.0 0.0 ns t eabwesu 5.5 5.8 ns t eabweh 0.0 0.0 ns t eabwdsu 5.5 5.8 ns t eabwdh 0.0 0.0 ns t eabwasu 2.1 2.7 ns t eabwah 0.0 0.0 ns t eabwo 9.5 11.8 ns
altera corporation 75 flex 10k embedded programmable logic family data sheet table 53. epf10k30 device interconnect timing microparameters note (1) symbol speed grade unit -3 -4 min max min max t din2ioe 6.9 8.7 ns t din2le 3.6 4.8 ns t din2data 5.5 7.2 ns t dclk2ioe 4.6 6.2 ns t dclk2le 3.6 4.8 ns t samelab 0.3 0.3 ns t samerow 3.3 3.7 ns t samecolumn 2.5 2.7 ns t diffrow 5.8 6.4 ns t tworows 9.1 10.1 ns t leperiph 6.2 7.1 ns t labcarry 0.4 0.6 ns t labcasc 2.4 3.0 ns table 54. epf10k40 device interconnect timing microparameters note (1) symbol speed grade unit -3 -4 min max min max t din2ioe 7.6 9.4 ns t din2le 3.6 4.8 ns t din2data 5.5 7.2 ns t dclk2ioe 4.6 6.2 ns t dclk2le 3.6 4.8 ns t samelab 0.3 0.3 ns t samerow 3.3 3.7 ns t samecolumn 3.1 3.2 ns t diffrow 6.4 6.4 ns t tworows 9.7 10.6 ns t leperiph 6.4 7.1 ns t labcarry 0.4 0.6 ns t labcasc 2.4 3.0 ns
76 altera corporation flex 10k embedded programmable logic family data sheet table 55. epf10k50 device interconnect timing microparameters note (1) symbol speed grade unit -3 -4 min max min max t din2ioe 8.4 10.2 ns t din2le 3.6 4.8 ns t din2data 5.5 7.2 ns t dclk2ioe 4.6 6.2 ns t dclk2le 3.6 4.8 ns t samelab 0.3 0.3 ns t samerow 3.3 3.7 ns t samecolumn 3.9 4.1 ns t diffrow 7.2 7.8 ns t tworows 10.5 11.5 ns t leperiph 7.5 8.2 ns t labcarry 0.4 0.6 ns t labcasc 2.4 3.0 ns table 56. epf10k30, epf10k40 & epf10k50 device external timing parameters note (1) symbol speed grade unit -3 -4 min max min max t drr 17.2 21.1 ns t insu (2) , (3) 5.7 6.4 ns t inh (3) 0.0 0.0 ns t outco (3) 2.0 8.8 2.0 11.2 ns
altera corporation 77 flex 10k embedded programmable logic family data sheet notes to tables: (1) all timing parameters are described in tables 32 through 39 in this data sheet. (2) using an le to register the signal may provide a lower setup time. (3) this parameter is specified by characterization. tables 58 through 64 show epf10k70 device internal and external timing parameters. table 57. epf10k30, epf10k40 & epf10k50 device external bidirectional timing parameters (1) symbol speed grade unit -3 -4 min max min max t insubidir 4.1 4.6 ns t inhbidir 0.0 0.0 ns t outcobidir 2.0 8.8 2.0 11.2 ns t xzbidir 12.3 15.0 ns t zxbidir 12.3 15.0 ns table 58. epf10k70 device le timing microparameters (part 1 of 2) note (1) symbol speed grade unit -2 -3 -4 min max min max min max t lut 1.3 1.5 2.0 ns t clut 0.4 0.4 0.5 ns t rlut 1.5 1.6 2.0 ns t packed 0.8 0.9 1.3 ns t en 0.8 0.9 1.2 ns t cico 0.2 0.2 0.3 ns t cgen 1.0 1.1 1.4 ns t cgenr 1.1 1.2 1.5 ns t casc 1.0 1.1 1.3 ns t c 0.7 0.8 1.0 ns t co 0.9 1.0 1.4 ns t comb 0.4 0.5 0.7 ns t su 1.9 2.1 2.6 ns t h 2.1 2.3 3.1 ns t pre 0.9 1.0 1.4 ns t clr 0.9 1.0 1.4 ns
78 altera corporation flex 10k embedded programmable logic family data sheet t ch 4.0 4.0 4.0 ns t cl 4.0 4.0 4.0 ns table 59. epf10k70 device ioe timing microparameters note (1) symbol speed grade unit -2 -3 -4 min max min max min max t iod 0.0 0.0 0.0 ns t ioc 0.4 0.5 0.7 ns t ioco 0.4 0.4 0.9 ns t iocomb 0.0 0.0 0.0 ns t iosu 4.5 5.0 6.2 ns t ioh 0.4 0.5 0.7 ns t ioclr 0.6 0.7 1.6 ns t od1 3.6 4.0 5.0 ns t od2 5.6 6.3 7.3 ns t od3 6.9 7.7 8.7 ns t xz 5.5 6.2 6.8 ns t zx1 5.5 6.2 6.8 ns t zx2 7.5 8.5 9.1 ns t zx3 8.8 9.9 10.5 ns t inreg 8.0 9.0 10.2 ns t iofd 7.2 8.1 10.3 ns t incomb 7.2 8.1 10.3 ns table 58. epf10k70 device le timing microparameters (part 2 of 2) note (1) symbol speed grade unit -2 -3 -4 min max min max min max
altera corporation 79 flex 10k embedded programmable logic family data sheet table 60. epf10k70 device eab internal microparameters note (1) symbol speed grade unit -2 -3 -4 min max min max min max t eabdata1 1.3 1.5 1.9 ns t eabdata2 4.3 4.8 6.0 ns t eabwe1 0.9 1.0 1.2 ns t eabwe2 4.5 5.0 6.2 ns t eabclk 0.9 1.0 2.2 ns t eabco 0.4 0.5 0.6 ns t eabbypass 1.3 1.5 1.9 ns t eabsu 1.3 1.5 1.8 ns t eabh 1.8 2.0 2.5 ns t aa 7.8 8.7 10.7 ns t wp 5.2 5.8 7.2 ns t wdsu 1.4 1.6 2.0 ns t wdh 0.3 0.3 0.4 ns t wasu 0.4 0.5 0.6 ns t wah 0.9 1.0 1.2 ns t wo 4.5 5.0 6.2 ns t dd 4.5 5.0 6.2 ns t eabout 0.4 0.5 0.6 ns t eabch 4.0 4.0 4.0 ns t eabcl 5.2 5.8 7.2 ns
80 altera corporation flex 10k embedded programmable logic family data sheet table 61. epf10k70 device eab internal timing macroparameters note (1) symbol speed grade unit -2 -3 -4 min max min max min max t eabaa 12.1 13.7 17.0 ns t eabrccomb 12.1 13.7 17.0 ns t eabrcreg 8.6 9.7 11.9 ns t eabwp 5.2 5.8 7.2 ns t eabwccomb 6.5 7.3 9.0 ns t eabwcreg 11.6 13.0 16.0 ns t eabdd 8.8 10.0 12.5 ns t eabdataco 1.7 2.0 3.4 ns t eabdatasu 4.7 5.3 5.6 ns t eabdatah 0.0 0.0 0.0 ns t eabwesu 4.9 5.5 5.8 ns t eabweh 0.0 0.0 0.0 ns t eabwdsu 1.8 2.1 2.7 ns t eabwdh 0.0 0.0 0.0 ns t eabwasu 4.1 4.7 5.8 ns t eabwah 0.0 0.0 0.0 ns t eabwo 8.4 9.5 11.8 ns
altera corporation 81 flex 10k embedded programmable logic family data sheet table 62. epf10k70 device interconnect timing microparameters note (1) symbol speed grade unit -2 -3 -4 min max min max min max t din2ioe 6.6 7.3 8.8 ns t din2le 4.2 4.8 6.0 ns t din2data 6.5 7.1 10.8 ns t dclk2ioe 5.5 6.2 7.7 ns t dclk2le 4.2 4.8 6.0 ns t samelab 0.4 0.4 0.5 ns t samerow 4.8 4.9 5.5 ns t samecolumn 3.3 3.4 3.7 ns t diffrow 8.1 8.3 9.2 ns t tworows 12.9 13.2 14.7 ns t leperiph 5.5 5.7 6.5 ns t labcarry 0.8 0.9 1.1 ns t labcasc 2.7 3.0 3.2 ns table 63. epf10k70 device external timing parameters note (1) symbol speed grade unit -2 -3 -4 min max min max min max t drr 17.2 19.1 24.2 ns t insu (2) , (3) 6.6 7.3 8.0 ns t inh (3) 0.0 0.0 0.0 ns t outco (3) 2.0 9.9 2.0 11.1 2.0 14.3 ns
82 altera corporation flex 10k embedded programmable logic family data sheet notes to tables: (1) all timing parameters are described in tables 32 through 39 in this data sheet. (2) using an le to register the signal may provide a lower setup time. (3) this parameter is specified by characterization. tables 65 through 71 show epf10k100 device internal and external timing parameters. table 64. epf10k70 device external bidirectional timing parameters note (1) symbol speed grade unit -2 -3 -4 min max min max min max t insubidir 7.4 8.1 10.4 ns t inhbidir 0.0 0.0 0.0 ns t outcobidir 2.0 9.9 2.0 11.1 2.0 14.3 ns t xzbidir 13.7 15.4 18.5 ns t zxbidir 13.7 15.4 18.5 ns table 65. epf10k100 device le timing microparameters (part 1 of 2) note (1) symbol speed grade unit -3dx -3 -4 min max min max min max t lut 1.5 1.5 2.0 ns t clut 0.4 0.4 0.5 ns t rlut 1.6 1.6 2.0 ns t packed 0.9 0.9 1.3 ns t en 0.9 0.9 1.2 ns t cico 0.2 0.2 0.3 ns t cgen 1.1 1.1 1.4 ns t cgenr 1.2 1.2 1.5 ns t casc 1.1 1.1 1.3 ns t c 0.8 0.8 1.0 ns t co 1.0 1.0 1.4 ns t comb 0.5 0.5 0.7 ns t su 2.1 2.1 2.6 ns t h 2.3 2.3 3.1 ns t pre 1.0 1.0 1.4 ns t clr 1.0 1.0 1.4 ns
altera corporation 83 flex 10k embedded programmable logic family data sheet t ch 4.0 4.0 4.0 ns t cl 4.0 4.0 4.0 ns table 66. epf10k100 device ioe timing microparameters note (1) symbol speed grade unit -3dx -3 -4 min max min max min max t iod 0.0 0.0 0.0 ns t ioc 0.5 0.5 0.7 ns t ioco 0.4 0.4 0.9 ns t iocomb 0.0 0.0 0.0 ns t iosu 5.5 5.5 6.7 ns t ioh 0.5 0.5 0.7 ns t ioclr 0.7 0.7 1.6 ns t od1 4.0 4.0 5.0 ns t od2 6.3 6.3 7.3 ns t od3 7.7 7.7 8.7 ns t xz 6.2 6.2 6.8 ns t zx1 6.2 6.2 6.8 ns t zx2 8.5 8.5 9.1 ns t zx3 9.9 9.9 10.5 ns t inreg without clocklock or clockboost circuitry 9.0 9.0 10.5 ns t inreg with clocklock or clockboost circuitry 3.0 ns t iofd 8.1 8.1 10.3 ns t incomb 8.1 8.1 10.3 ns table 65. epf10k100 device le timing microparameters (part 2 of 2) note (1) symbol speed grade unit -3dx -3 -4 min max min max min max
84 altera corporation flex 10k embedded programmable logic family data sheet table 67. epf10k100 device eab internal microparameters note (1) symbol speed grade unit -3dx -3 -4 min max min max min max t eabdata1 1.5 1.5 1.9 ns t eabdata2 4.8 4.8 6.0 ns t eabwe1 1.0 1.0 1.2 ns t eabwe2 5.0 5.0 6.2 ns t eabclk 1.0 1.0 2.2 ns t eabco 0.5 0.5 0.6 ns t eabbypass 1.5 1.5 1.9 ns t eabsu 1.5 1.5 1.8 ns t eabh 2.0 2.0 2.5 ns t aa 8.7 8.7 10.7 ns t wp 5.8 5.8 7.2 ns t wdsu 1.6 1.6 2.0 ns t wdh 0.3 0.3 0.4 ns t wasu 0.5 0.5 0.6 ns t wah 1.0 1.0 1.2 ns t wo 5.0 5.0 6.2 ns t dd 5.0 5.0 6.2 ns t eabout 0.5 0.5 0.6 ns t eabch 4.0 4.0 4.0 ns t eabcl 5.8 5.8 7.2 ns
altera corporation 85 flex 10k embedded programmable logic family data sheet table 68. epf10k100 device eab internal timing macroparameters note (1) symbol speed grade unit -3dx -3 -4 min max min max min max t eabaa 13.7 13.7 17.0 ns t eabrccomb 13.7 13.7 17.0 ns t eabrcreg 9.7 9.7 11.9 ns t eabwp 5.8 5.8 7.2 ns t eabwccomb 7.3 7.3 9.0 ns t eabwcreg 13.0 13.0 16.0 ns t eabdd 10.0 10.0 12.5 ns t eabdataco 2.0 2.0 3.4 ns t eabdatasu 5.3 5.3 5.6 ns t eabdatah 0.0 0.0 0.0 ns t eabwesu 5.5 5.5 5.8 ns t eabweh 0.0 0.0 0.0 ns t eabwdsu 5.5 5.5 5.8 ns t eabwdh 0.0 0.0 0.0 ns t eabwasu 2.1 2.1 2.7 ns t eabwah 0.0 0.0 0.0 ns t eabwo 9.5 9.5 11.8 ns
86 altera corporation flex 10k embedded programmable logic family data sheet table 69. epf10k100 device interconnect timing microparameters note (1) symbol speed grade unit -3dx -3 -4 min max min max min max t din2ioe 10.3 10.3 12.2 ns t din2le 4.8 4.8 6.0 ns t din2data 7.3 7.3 11.0 ns t dclk2ioe without clocklock or clockboost circuitry 6.2 6.2 7.7 ns t dclk2ioe with clocklock or clockboost circuitry 2.3 ns t dclk2le without clocklock or clockboost circuitry 4.8 4.8 6.0 ns t dclk2le with clocklock or clockboost circuitry 2.3 ns t samelab 0.4 0.4 0.5 ns t samerow 4.9 4.9 5.5 ns t samecolumn 5.1 5.1 5.4 ns t diffrow 10.0 10.0 10.9 ns t tworows 14.9 14.9 16.4 ns t leperiph 6.9 6.9 8.1 ns t labcarry 0.9 0.9 1.1 ns t labcasc 3.0 3.0 3.2 ns
altera corporation 87 flex 10k embedded programmable logic family data sheet notes to tables: (1) all timing parameters are described in tables 32 through 39 in this data sheet. (2) using an le to register the signal may provide a lower setup time. (3) this parameter is specified by characterization. (4) this parameter is measured without the use of the clocklock or clockboost circuits. (5) this parameter is measured with the use of the clocklock or clockboost circuits. table 70. epf10k100 device external timing parameters note (1) symbol speed grade unit -3dx -3 -4 min max min max min max t drr 19.1 19.1 24.2 ns t insu (2) , (3) , (4) 7.8 7.8 8.5 ns t outco (3) , (4) 2.0 11.1 2.0 11.1 2.0 14.3 ns t inh (3) 0.0 0.0 0.0 ns t insu (2) , (3) , (5) 6.2 ns t outco (3) , (5) 2.0 6.7 ns table 71. epf10k100 device external bidirectional timing parameters note (1) symbol speed grade unit -3dx -3 -4 min max min max min max t insubidir (4) 8.1 8.1 10.4 ns t inhbidir (4) 0.0 0.0 0.0 ns t outcobidir (4) 2.0 11.1 2.0 11.1 2.0 14.3 ns t xzbidir (4) 15.3 15.3 18.4 ns t zxbidir (4) 15.3 15.3 18.4 ns t insubidir (5) 9.1 ns t inhbidir (5) 0.0 ns t outcobidir (5) 2.0 7.2 ns t xzbidir (5) 14.3 ns t zxbidir (5) 14.3 ns
88 altera corporation flex 10k embedded programmable logic family data sheet tables 72 through 78 show epf10k50v device internal and external timing parameters. table 72. epf10k50v device le timing microparameters note (1) symbol speed grade unit -1 -2 -3 -4 min max min max min max min max t lut 0.9 1.0 1.3 1.6 ns t clut 0.1 0.5 0.6 0.6 ns t rlut 0.5 0.8 0.9 1.0 ns t packed 0.4 0.4 0.5 0.7 ns t en 0.7 0.9 1.1 1.4 ns t cico 0.2 0.2 0.2 0.3 ns t cgen 0.8 0.7 0.8 1.2 ns t cgenr 0.4 0.3 0.3 0.4 ns t casc 0.7 0.7 0.8 0.9 ns t c 0.3 1.0 1.3 1.5 ns t co 0.5 0.7 0.9 1.0 ns t comb 0.4 0.4 0.5 0.6 ns t su 0.8 1.6 2.2 2.5 ns t h 0.5 0.8 1.0 1.4 ns t pre 0.8 0.4 0.5 0.5 ns t clr 0.8 0.4 0.5 0.5 ns t ch 2.0 4.0 4.0 4.0 ns t cl 2.0 4.0 4.0 4.0 ns
altera corporation 89 flex 10k embedded programmable logic family data sheet table 73. epf10k50v device ioe timing microparameters note (1) symbol speed grade unit -1 -2 -3 -4 min max min max min max min max t iod 1.2 1.6 1.9 2.1 ns t ioc 0.3 0.4 0.5 0.5 ns t ioco 0.3 0.3 0.4 0.4 ns t iocomb 0.0 0.0 0.0 0.0 ns t iosu 2.8 2.8 3.4 3.9 ns t ioh 0.7 0.8 1.0 1.4 ns t ioclr 0.5 0.6 0.7 0.7 ns t od1 2.8 3.2 3.9 4.7 ns t od2 ns t od3 6.5 6.9 7.6 8.4 ns t xz 2.8 3.1 3.8 4.6 ns t zx1 2.8 3.1 3.8 4.6 ns t zx2 ns t zx3 6.5 6.8 7.5 8.3 ns t inreg 5.0 5.7 7.0 9.0 ns t iofd 1.5 1.9 2.3 2.7 ns t incomb 1.5 1.9 2.3 2.7 ns
90 altera corporation flex 10k embedded programmable logic family data sheet table 74. epf10k50v device eab internal microparameters note (1) symbol speed grade unit -1 -2 -3 -4 min max min max min max min max t eabdata1 1.7 2.8 3.4 4.6 ns t eabdata2 4.9 3.9 4.8 5.9 ns t eabwe1 0.0 2.5 3.0 3.7 ns t eabwe2 4.0 4.1 5.0 6.2 ns t eabclk 0.4 0.8 1.0 1.2 ns t eabco 0.1 0.2 0.3 0.4 ns t eabbypass 0.9 1.1 1.3 1.6 ns t eabsu 0.8 1.5 1.8 2.2 ns t eabh 0.8 1.6 2.0 2.5 ns t aa 5.5 8.2 10.0 12.4 ns t wp 6.0 4.9 6.0 7.4 ns t wdsu 0.1 0.8 1.0 1.2 ns t wdh 0.1 0.2 0.3 0.4 ns t wasu 0.1 0.4 0.5 0.6 ns t wah 0.1 0.8 1.0 1.2 ns t wo 2.8 4.3 5.3 6.5 ns t dd 2.8 4.3 5.3 6.5 ns t eabout 0.5 0.4 0.5 0.6 ns t eabch 2.0 4.0 4.0 4.0 ns t eabcl 6.0 4.9 6.0 7.4 ns
altera corporation 91 flex 10k embedded programmable logic family data sheet table 75. epf10k50v device eab internal timing macroparameters note (1) symbol speed grade unit -1 -2 -3 -4 min max min max min max min max t eabaa 9.5 13.6 16.5 20.8 ns t eabrccomb 9.5 13.6 16.5 20.8 ns t eabrcreg 6.1 8.8 10.8 13.4 ns t eabwp 6.0 4.9 6.0 7.4 ns t eabwccomb 6.2 6.1 7.5 9.2 ns t eabwcreg 12.0 11.6 14.2 17.4 ns t eabdd 6.8 9.7 11.8 14.9 ns t eabdataco 1.0 1.4 1.8 2.2 ns t eabdatasu 5.3 4.6 5.6 6.9 ns t eabdatah 0.0 0.0 0.0 0.0 ns t eabwesu 4.4 4.8 5.8 7.2 ns t eabweh 0.0 0.0 0.0 0.0 ns t eabwdsu 1.8 1.1 1.4 2.1 ns t eabwdh 0.0 0.0 0.0 0.0 ns t eabwasu 4.5 4.6 5.6 7.4 ns t eabwah 0.0 0.0 0.0 0.0 ns t eabwo 5.1 9.4 11.4 14.0 ns
92 altera corporation flex 10k embedded programmable logic family data sheet table 76. epf10k50v device interconnect timing microparameters note (1) symbol speed grade unit -1 -2 -3 -4 min max min max min max min max t din2ioe 4.7 6.0 7.1 8.2 ns t din2le 2.5 2.6 3.1 3.9 ns t din2data 4.4 5.9 6.8 7.7 ns t dclk2ioe 2.5 3.9 4.7 5.5 ns t dclk2le 2.5 2.6 3.1 3.9 ns t samelab 0.2 0.2 0.3 0.3 ns t samerow 2.8 3.0 3.2 3.4 ns t samecolumn 3.0 3.2 3.4 3.6 ns t diffrow 5.8 6.2 6.6 7.0 ns t tworows 8.6 9.2 9.8 10.4 ns t leperiph 4.5 5.5 6.1 7.0 ns t labcarry 0.3 0.4 0.5 0.7 ns t labcasc 0.0 1.3 1.6 2.0 ns table 77. epf10k50v device external timing parameters note (1) symbol speed grade unit -1 -2 -3 -4 min max min max min max min max t drr 11.2 14.0 17.2 21.1 ns t insu (2) , (3) 5.5 4.2 5.2 6.9 ns t inh (3) 0.0 0.0 0.0 0.0 ns t outco (3) 2.0 5.9 2.0 7.8 2.0 9.5 2.0 11.1 ns
altera corporation 93 flex 10k embedded programmable logic family data sheet notes to tables: (1) all timing parameters are described in tables 32 through 39 in this data sheet. (2) using an le to register the signal may provide a lower setup time. (3) this parameter is specified by characterization. tables 79 through 85 show epf10k130v device internal and external timing parameters. table 78. epf10k50v device external bidirectional timing parameters note (1) symbol speed grade unit -1 -2 -3 -4 min max min max min max min max t insubidir 2.0 2.8 3.5 4.1 ns t inhbidir 0.0 0.0 0.0 0.0 ns t outcobidir 2.0 5.9 2.0 7.8 2.0 9.5 2.0 11.1 ns t xzbidir 8.0 9.8 11.8 14.3 ns t zxbidir 8.0 9.8 11.8 14.3 ns table 79. epf10k130v device le timing microparameters (part 1 of 2) note (1) symbol speed grade unit -2 -3 -4 min max min max min max t lut 1.3 1.8 2.3 ns t clut 0.5 0.7 0.9 ns t rlut 1.2 1.7 2.2 ns t packed 0.5 0.6 0.7 ns t en 0.6 0.8 1.0 ns t cico 0.2 0.3 0.4 ns t cgen 0.3 0.4 0.5 ns t cgenr 0.7 1.0 1.3 ns t casc 0.9 1.2 1.5 ns t c 1.9 2.4 3.0 ns t co 0.6 0.9 1.1 ns t comb 0.5 0.7 0.9 ns t su 0.2 0.2 0.3 ns t h 0.0 0.0 0.0 ns t pre 2.4 3.1 3.9 ns t clr 2.4 3.1 3.9 ns
94 altera corporation flex 10k embedded programmable logic family data sheet t ch 4.0 4.0 4.0 ns t cl 4.0 4.0 4.0 ns table 80. epf10k130v device ioe timing microparameters note (1) symbol speed grade unit -2 -3 -4 min max min max min max t iod 1.3 1.6 2.0 ns t ioc 0.4 0.5 0.7 ns t ioco 0.3 0.4 0.5 ns t iocomb 0.0 0.0 0.0 ns t iosu 2.6 3.3 3.8 ns t ioh 0.0 0.0 0.0 ns t ioclr 1.7 2.2 2.7 ns t od1 3.5 4.4 5.0 ns t od2 ns t od3 8.2 8.1 9.7 ns t xz 4.9 6.3 7.4 ns t zx1 4.9 6.3 7.4 ns t zx2 ns t zx3 9.6 10.0 12.1 ns t inreg 7.9 10.0 12.6 ns t iofd 6.2 7.9 9.9 ns t incomb 6.2 7.9 9.9 ns table 79. epf10k130v device le timing microparameters (part 2 of 2) note (1) symbol speed grade unit -2 -3 -4 min max min max min max
altera corporation 95 flex 10k embedded programmable logic family data sheet table 81. epf10k130v device eab internal microparameters note (1) symbol speed grade unit -2 -3 -4 min max min max min max t eabdata1 1.9 2.4 2.4 ns t eabdata2 3.7 4.7 4.7 ns t eabwe1 1.9 2.4 2.4 ns t eabwe2 3.7 4.7 4.7 ns t eabclk 0.7 0.9 0.9 ns t eabco 0.5 0.6 0.6 ns t eabbypass 0.6 0.8 0.8 ns t eabsu 1.4 1.8 1.8 ns t eabh 0.0 0.0 0.0 ns t aa 5.6 7.1 7.1 ns t wp 3.7 4.7 4.7 ns t wdsu 4.6 5.9 5.9 ns t wdh 0.0 0.0 0.0 ns t wasu 3.9 5.0 5.0 ns t wah 0.0 0.0 0.0 ns t wo 5.6 7.1 7.1 ns t dd 5.6 7.1 7.1 ns t eabout 2.4 3.1 3.1 ns t eabch 4.0 4.0 4.0 ns t eabcl 4.0 4.7 4.7 ns
96 altera corporation flex 10k embedded programmable logic family data sheet table 82. epf10k130v device eab internal timing macroparameters note (1) symbol speed grade unit -2 -3 -4 min max min max min max t eabaa 11.2 14.2 14.2 ns t eabrccomb 11.1 14.2 14.2 ns t eabrcreg 8.5 10.8 10.8 ns t eabwp 3.7 4.7 4.7 ns t eabwccomb 7.6 9.7 9.7 ns t eabwcreg 14.0 17.8 17.8 ns t eabdd 11.1 14.2 14.2 ns t eabdataco 3.6 4.6 4.6 ns t eabdatasu 4.4 5.6 5.6 ns t eabdatah 0.0 0.0 0.0 ns t eabwesu 4.4 5.6 5.6 ns t eabweh 0.0 0.0 0.0 ns t eabwdsu 4.6 5.9 5.9 ns t eabwdh 0.0 0.0 0.0 ns t eabwasu 3.9 5.0 5.0 ns t eabwah 0.0 0.0 0.0 ns t eabwo 11.1 14.2 14.2 ns
altera corporation 97 flex 10k embedded programmable logic family data sheet table 83. epf10k130v device interconnect timing microparameters note (1) symbol speed grade unit -2 -3 -4 min max min max min max t din2ioe 8.0 9.0 9.5 ns t din2le 2.4 3.0 3.1 ns t din2data 5.0 6.3 7.4 ns t dclk2ioe 3.6 4.6 5.1 ns t dclk2le 2.4 3.0 3.1 ns t samelab 0.4 0.6 0.8 ns t samerow 4.5 5.3 6.5 ns t samecolumn 9.0 9.5 9.7 ns t diffrow 13.5 14.8 16.2 ns t tworows 18.0 20.1 22.7 ns t leperiph 8.1 8.6 9.5 ns t labcarry 0.6 0.8 1.0 ns t labcasc 0.8 1.0 1.2 ns table 84. epf10k130v device external timing parameters note (1) symbol speed grade unit -2 -3 -4 min max min max min max t drr 15.0 19.1 24.2 ns t insu (2) , (3) 6.9 8.6 11.0 ns t inh (3) 0.0 0.0 0.0 ns t outco (3) 2.0 7.8 2.0 9.9 2.0 11.3 ns
98 altera corporation flex 10k embedded programmable logic family data sheet notes to tables: (1) all timing parameters are described in tables 32 through 39 in this data sheet. (2) using an le to register the signal may provide a lower setup time. (3) this parameter is specified by characterization. tables 86 through 92 show epf10k10a device internal and external timing parameters. table 85. epf10k130v device external bidirectional timing parameters note (1) symbol speed grade unit -2 -3 -4 min max min max min max t insubidir 6.7 8.5 10.8 ns t inhbidir 0.0 0.0 0.0 ns t outcobidir 2.0 6.9 2.0 8.8 2.0 10.2 ns t xzbidir 12.9 16.4 19.3 ns t zxbidir 12.9 16.4 19.3 ns table 86. epf10k10a device le timing microparameters (part 1 of 2) note (1) symbol speed grade unit -1 -2 -3 min max min max min max t lut 0.9 1.2 1.6 ns t clut 1.2 1.4 1.9 ns t rlut 1.9 2.3 3.0 ns t packed 0.6 0.7 0.9 ns t en 0.5 0.6 0.8 ns t cico 02 0.3 0.4 ns t cgen 0.7 0.9 1.1 ns t cgenr 0.7 0.9 1.1 ns t casc 1.0 1.2 1.7 ns t c 1.2 1.4 1.9 ns t co 0.5 0.6 0.8 ns t comb 0.5 0.6 0.8 ns t su 1.1 1.3 1.7 ns t h 0.6 0.7 0.9 ns t pre 0.5 0.6 0.9 ns t clr 0.5 0.6 0.9 ns
altera corporation 99 flex 10k embedded programmable logic family data sheet t ch 3.0 3.5 4.0 ns t cl 3.0 3.5 4.0 ns table 87. epf10k10a device ioe timing microparameters note (1) symbol speed grade unit -1 -2 -3 min max min max min max t iod 1.3 1.5 2.0 ns t ioc 0.2 0.3 0.3 ns t ioco 0.2 0.3 0.4 ns t iocomb 0.6 0.7 0.9 ns t iosu 0.8 1.0 1.3 ns t ioh 0.8 1.0 1.3 ns t ioclr 1.2 1.4 1.9 ns t od1 1.2 1.4 1.9 ns t od2 2.9 3.5 4.7 ns t od3 6.6 7.8 10.5 ns t xz 1.2 1.4 1.9 ns t zx1 1.2 1.4 1.9 ns t zx2 2.9 3.5 4.7 ns t zx3 6.6 7.8 10.5 ns t inreg 5.2 6.3 8.4 ns t iofd 3.1 3.8 5.0 ns t incomb 3.1 3.8 5.0 ns table 86. epf10k10a device le timing microparameters (part 2 of 2) note (1) symbol speed grade unit -1 -2 -3 min max min max min max
100 altera corporation flex 10k embedded programmable logic family data sheet table 88. epf10k10a device eab internal microparameters note (1) symbol speed grade unit -1 -2 -3 min max min max min max t eabdata1 3.3 3.9 5.2 ns t eabdata2 1.0 1.3 1.7 ns t eabwe1 2.6 3.1 4.1 ns t eabwe2 2.7 3.2 4.3 ns t eabclk 0.0 0.0 0.0 ns t eabco 1.2 1.4 1.8 ns t eabbypass 0.1 0.2 0.2 ns t eabsu 1.4 1.7 2.2 ns t eabh 0.1 0.1 0.1 ns t aa 4.5 5.4 7.3 ns t wp 2.0 2.4 3.2 ns t wdsu 0.7 0.8 1.1 ns t wdh 0.5 0.6 0.7 ns t wasu 0.6 0.7 0.9 ns t wah 0.9 1.1 1.5 ns t wo 3.3 3.9 5.2 ns t dd 3.3 3.9 5.2 ns t eabout 0.1 0.1 0.2 ns t eabch 3.0 3.5 4.0 ns t eabcl 3.03 3.5 4.0 ns
altera corporation 101 flex 10k embedded programmable logic family data sheet table 89. epf10k10a device eab internal timing macroparameters note (1) symbol speed grade unit -1 -2 -3 min max min max min max t eabaa 8.1 9.8 13.1 ns t eabrccomb 8.1 9.8 13.1 ns t eabrcreg 5.8 6.9 9.3 ns t eabwp 2.0 2.4 3.2 ns t eabwccomb 3.5 4.2 5.6 ns t eabwcreg 9.4 11.2 14.8 ns t eabdd 6.9 8.3 11.0 ns t eabdataco 1.3 1.5 2.0 ns t eabdatasu 2.4 3.0 3.9 ns t eabdatah 0.0 0.0 0.0 ns t eabwesu 4.1 4.9 6.5 ns t eabweh 0.0 0.0 0.0 ns t eabwdsu 1.4 1.6 2.2 ns t eabwdh 0.0 0.0 0.0 ns t eabwasu 2.5 3.0 4.1 ns t eabwah 0.0 0.0 0.0 ns t eabwo 6.2 7.5 9.9 ns
102 altera corporation flex 10k embedded programmable logic family data sheet table 90. epf10k10a device interconnect timing microparameters note (1) symbol speed grade unit -1 -2 -3 min max min max min max t din2ioe 4.2 5.0 6.5 ns t din2le 2.2 2.6 3.4 ns t din2data 4.3 5.2 7.1 ns t dclk2ioe 4.2 4.9 6.6 ns t dclk2le 2.2 2.6 3.4 ns t samelab 0.1 0.1 0.2 ns t samerow 2.2 2.4 2.9 ns t samecolumn 0.8 1.0 1.4 ns t diffrow 3.0 3.4 4.3 ns t tworows 5.2 5.8 7.2 ns t leperiph 1.8 2.2 2.8 ns t labcarry 0.5 0.5 0.7 ns t labcasc 0.9 1.0 1.5 ns table 91. epf10k10a external reference timing parameters note (1) symbol speed grade unit -1 -2 -3 min max min max min max t drr 10.0 12.0 16.0 ns t insu (2) , (3) 1.6 2.1 2.8 ns t inh (3) 0.0 0.0 0.0 ns t outco (3) 2.0 5.8 2.0 6.9 2.0 9.2 ns
altera corporation 103 flex 10k embedded programmable logic family data sheet notes to tables: (1) all timing parameters are described in tables 32 through 39 in this data sheet. (2) using an le to register the signal may provide a lower setup time. (3) this parameter is specified by characterization. tables 93 through 99 show epf10k30a device internal and external timing parameters. table 92. epf10k10a device external bidirectional timing parameters note (1) symbol speed grade unit -2 -3 -4 min max min max min max t insubidir 2.4 3.3 4.5 ns t inhbidir 0.0 0.0 0.0 ns t outcobidir 2.0 5.8 2.0 6.9 2.0 9.2 ns t xzbidir 6.3 7.5 9.9 ns t zxbidir 6.3 7.5 9.9 ns table 93. epf10k30a device le timing microparameters (part 1 of 2) note (1) symbol speed grade unit -1 -2 -3 min max min max min max t lut 0.8 1.1 1.5 ns t clut 0.6 0.7 1.0 ns t rlut 1.2 1.5 2.0 ns t packed 0.6 0.6 1.0 ns t en 1.3 1.5 2.0 ns t cico 0.2 0.3 0.4 ns t cgen 0.8 1.0 1.3 ns t cgenr 0.6 0.8 1.0 ns t casc 0.9 1.1 1.4 ns t c 1.1 1.3 1.7 ns t co 0.4 0.6 0.7 ns t comb 0.6 0.7 0.9 ns t su 0.9 0.9 1.4 ns t h 1.1 1.3 1.7 ns t pre 0.5 0.6 0.8 ns t clr 0.5 0.6 0.8 ns
104 altera corporation flex 10k embedded programmable logic family data sheet t ch 3.0 3.5 4.0 ns t cl 3.0 3.5 4.0 ns table 94. epf10k30a device ioe timing microparameters note (1) symbol speed grade unit -1 -2 -3 min max min max min max t iod 2.2 2.6 3.4 ns t ioc 0.3 0.3 0.5 ns t ioco 0.2 0.2 0.3 ns t iocomb 0.5 0.6 0.8 ns t iosu 1.4 1.7 2.2 ns t ioh 0.9 1.1 1.4 ns t ioclr 0.7 0.8 1.0 ns t od1 1.9 2.2 2.9 ns t od2 4.8 5.6 7.3 ns t od3 7.0 8.2 10.8 ns t xz 2.2 2.6 3.4 ns t zx1 2.2 2.6 3.4 ns t zx2 5.1 6.0 7.8 ns t zx3 7.3 8.6 11.3 ns t inreg 4.4 5.2 6.8 ns t iofd 3.8 4.5 5.9 ns t incomb 3.8 4.5 5.9 ns table 93. epf10k30a device le timing microparameters (part 2 of 2) note (1) symbol speed grade unit -1 -2 -3 min max min max min max
altera corporation 105 flex 10k embedded programmable logic family data sheet table 95. epf10k30a device eab internal microparameters note (1) symbol speed grade unit -1 -2 -3 min max min max min max t eabdata1 5.5 6.5 8.5 ns t eabdata2 1.1 1.3 1.8 ns t eabwe1 2.4 2.8 3.7 ns t eabwe2 2.1 2.5 3.2 ns t eabclk 0.0 0.0 0.2 ns t eabco 1.7 2.0 2.6 ns t eabbypass 0.0 0.0 0.3 ns t eabsu 1.2 1.4 1.9 ns t eabh 0.1 0.1 0.3 ns t aa 4.2 5.0 6.5 ns t wp 3.8 4.5 5.9 ns t wdsu 0.1 0.1 0.2 ns t wdh 0.1 0.1 0.2 ns t wasu 0.1 0.1 0.2 ns t wah 0.1 0.1 0.2 ns t wo 3.7 4.4 6.4 ns t dd 3.7 4.4 6.4 ns t eabout 0.0 0.1 0.6 ns t eabch 3.0 3.5 4.0 ns t eabcl 3.8 4.5 5.9 ns
106 altera corporation flex 10k embedded programmable logic family data sheet table 96. epf10k30a device eab internal timing macroparameters note (1) symbol speed grade unit -1 -2 -3 min max min max min max t eabaa 9.7 11.6 16.2 ns t eabrccomb 9.7 11.6 16.2 ns t eabrcreg 5.9 7.1 9.7 ns t eabwp 3.8 4.5 5.9 ns t eabwccomb 4.0 4.7 6.3 ns t eabwcreg 9.8 11.6 16.6 ns t eabdd 9.2 11.0 16.1 ns t eabdataco 1.7 2.1 3.4 ns t eabdatasu 2.3 2.7 3.5 ns t eabdatah 0.0 0.0 0.0 ns t eabwesu 3.3 3.9 4.9 ns t eabweh 0.0 0.0 0.0 ns t eabwdsu 3.2 3.8 5.0 ns t eabwdh 0.0 0.0 0.0 ns t eabwasu 3.7 4.4 5.1 ns t eabwah 0.0 0.0 0.0 ns t eabwo 6.1 7.3 11.3 ns
altera corporation 107 flex 10k embedded programmable logic family data sheet table 97. epf10k30a device interconnect timing microparameters note (1) symbol speed grade unit -1 -2 -3 min max min max min max t din2ioe 3.9 4.4 5.1 ns t din2le 1.2 1.5 1.9 ns t din2data 3.2 3.6 4.5 ns t dclk2ioe 3.0 3.5 4.6 ns t dclk2le 1.2 1.5 1.9 ns t samelab 0.1 0.1 0.2 ns t samerow 2.3 2.4 2.7 ns t samecolumn 1.3 1.4 1.9 ns t diffrow 3.6 3.8 4.6 ns t tworows 5.9 6.2 7.3 ns t leperiph 3.5 3.8 4.1 ns t labcarry 0.3 0.4 0.5 ns t labcasc 0.9 1.1 1.4 ns table 98. epf10k30a external reference timing parameters note (1) symbol speed grade unit -1 -2 -3 min max min max min max t drr 11.0 13.0 17.0 ns t insu (2) , (3) 2.5 3.1 3.9 ns t inh (3) 0.0 0.0 0.0 ns t outco (3) 2.0 5.4 2.0 6.2 2.0 8.3 ns
108 altera corporation flex 10k embedded programmable logic family data sheet notes to tables: (1) all timing parameters are described in tables 32 through 39 in this data sheet. (2) using an le to register the signal may provide a lower setup time. (3) this parameter is specified by characterization. tables 100 through 106 show epf10k100a device internal and external timing parameters. table 99. epf10k30a device external bidirectional timing parameters note (1) symbol speed grade unit -1 -2 -3 min max min max min max t insubidir 4.2 4.9 6.8 ns t inhbidir 0.0 0.0 0.0 ns t outcobidir 2.0 5.4 2.0 6.2 2.0 8.3 ns t xzbidir 6.2 7.5 9.8 ns t zxbidir 6.2 7.5 9.8 ns table 100. epf10k100a device le timing microparameters (part 1 of 2) note (1) symbol speed grade unit -1 -2 -3 min max min max min max t lut 1.0 1.2 1.4 ns t clut 0.8 0.9 1.1 ns t rlut 1.4 1.6 1.9 ns t packed 0.4 0.5 0.5 ns t en 0.6 0.7 0.8 ns t cico 0.2 0.2 0.3 ns t cgen 0.4 0.4 0.6 ns t cgenr 0.6 0.7 0.8 ns t casc 0.7 0.9 1.0 ns t c 0.9 1.0 1.2 ns t co 0.2 0.3 0.3 ns t comb 0.6 0.7 0.8 ns t su 0.8 1.0 1.2 ns t h 0.3 0.5 0.5 ns t pre 0.3 0.3 0.4 ns t clr 0.3 0.3 0.4 ns
altera corporation 109 flex 10k embedded programmable logic family data sheet t ch 2.5 3.5 4.0 ns t cl 2.5 3.5 4.0 ns table 101. epf10k100a device ioe timing microparameters note (1) symbol speed grade unit -1 -2 -3 min max min max min max t iod 2.5 2.9 3.4 ns t ioc 0.3 0.3 0.4 ns t ioco 0.2 0.2 0.3 ns t iocomb 0.5 0.6 0.7 ns t iosu 1.3 1.7 1.8 ns t ioh 0.2 0.2 0.3 ns t ioclr 1.0 1.2 1.4 ns t od1 2.2 2.6 3.0 ns t od2 4.5 5.3 6.1 ns t od3 6.8 7.9 9.3 ns t xz 2.7 3.1 3.7 ns t zx1 2.7 3.1 3.7 ns t zx2 5.0 5.8 6.8 ns t zx3 7.3 8.4 10.0 ns t inreg 5.3 6.1 7.2 ns t iofd 4.7 5.5 6.4 ns t incomb 4.7 5.5 6.4 ns table 100. epf10k100a device le timing microparameters (part 2 of 2) note (1) symbol speed grade unit -1 -2 -3 min max min max min max
110 altera corporation flex 10k embedded programmable logic family data sheet table 102. epf10k100a device eab internal microparameters note (1) symbol speed grade unit -1 -2 -3 min max min max min max t eabdata1 1.8 2.1 2.4 ns t eabdata2 3.2 3.7 4.4 ns t eabwe1 0.8 0.9 1.1 ns t eabwe2 2.3 2.7 3.1 ns t eabclk 0.8 0.9 1.1 ns t eabco 1.0 1.1 1.4 ns t eabbypass 0.3 0.3 0.4 ns t eabsu 1.3 1.5 1.8 ns t eabh 0.4 0.5 0.5 ns t aa 4.1 4.8 5.6 ns t wp 3.2 3.7 4.4 ns t wdsu 2.4 2.8 3.3 ns t wdh 0.2 0.2 0.3 ns t wasu 0.2 0.2 0.3 ns t wah 0.0 0.0 0.0 ns t wo 3.4 3.9 4.6 ns t dd 3.4 3.9 4.6 ns t eabout 0.3 0.3 0.4 ns t eabch 2.5 3.5 4.0 ns t eabcl 3.2 3.7 4.4 ns
altera corporation 111 flex 10k embedded programmable logic family data sheet table 103. epf10k100a device eab internal timing macroparameters note (1) symbol speed grade unit -1 -2 -3 min max min max min max t eabaa 6.8 7.8 9.2 ns t eabrccomb 6.8 7.8 9.2 ns t eabrcreg 5.4 6.2 7.4 ns t eabwp 3.2 3.7 4.4 ns t eabwccomb 3.4 3.9 4.7 ns t eabwcreg 9.4 10.8 12.8 ns t eabdd 6.1 6.9 8.2 ns t eabdataco 2.1 2.3 2.9 ns t eabdatasu 3.7 4.3 5.1 ns t eabdatah 0.0 0.0 0.0 ns t eabwesu 2.8 3.3 3.8 ns t eabweh 0.0 0.0 0.0 ns t eabwdsu 3.4 4.0 4.6 ns t eabwdh 0.0 0.0 0.0 ns t eabwasu 1.9 2.3 2.6 ns t eabwah 0.0 0.0 0.0 ns t eabwo 5.1 5.7 6.9 ns
112 altera corporation flex 10k embedded programmable logic family data sheet table 104. epf10k100a device interconnect timing microparameters note (1) symbol speed grade unit -1 -2 -3 min max min max min max t din2ioe 4.8 5.4 6.0 ns t din2le 2.0 2.4 2.7 ns t din2data 2.4 2.7 2.9 ns t dclk2ioe 2.6 3.0 3.5 ns t dclk2le 2.0 2.4 2.7 ns t samelab 0.1 0.1 0.1 ns t samerow 1.5 1.7 1.9 ns t samecolumn 5.5 6.5 7.4 ns t diffrow 7.0 8.2 9.3 ns t tworows 8.5 9.9 11.2 ns t leperiph 3.9 4.2 4.5 ns t labcarry 0.2 0.2 0.3 ns t labcasc 0.4 0.5 0.6 ns table 105. epf10k100a device external timing parameters note (1) symbol speed grade unit -1 -2 -3 min max min max min max t drr 12.5 14.5 17.0 ns t insu (2) , (3) 3.7 4.5 5.1 ns t inh (3) 0.0 0.0 0.0 ns t outco (3) 2.0 5.3 2.0 6.1 2.0 7.2 ns
altera corporation 113 flex 10k embedded programmable logic family data sheet notes to tables: (1) all timing parameters are described in tables 32 through 39 in this data sheet. (2) using an le to register the signal may provide a lower setup time. (3) this parameter is specified by characterization. tables 107 through 113 show epf10k250a device internal and external timing parameters. table 106. epf10k100a device external bidirectional timing parameters note (1) symbol speed grade unit -1 -2 -3 min max min max min max t insubidir 4.9 5.8 6.8 ns t inhbidir 0.0 0.0 0.0 ns t outcobidir 2.0 5.3 2.0 6.1 2.0 7.2 ns t xzbidir 7.4 8.6 10.1 ns t zxbidir 7.4 8.6 10.1 ns table 107. epf10k250a device le timing microparameters (part 1 of 2) note (1) symbol speed grade unit -1 -2 -3 min max min max min max t lut 0.9 1.0 1.4 ns t clut 1.2 1.3 1.6 ns t rlut 2.0 2.3 2.7 ns t packed 0.4 0.4 0.5 ns t en 1.4 1.6 1.9 ns t cico 0.2 0.3 0.3 ns t cgen 0.4 0.6 0.6 ns t cgenr 0.8 1.0 1.1 ns t casc 0.7 0.8 1.0 ns t c 1.2 1.3 1.6 ns t co 0.6 0.7 0.9 ns t comb 0.5 0.6 0.7 ns t su 1.2 1.4 1.7 ns t h 1.2 1.3 1.6 ns t pre 0.7 0.8 0.9 ns t clr 0.7 0.8 0.9 ns
114 altera corporation flex 10k embedded programmable logic family data sheet t ch 2.5 3.0 3.5 ns t cl 2.5 3.0 3.5 ns table 108. epf10k250a device ioe timing microparameters note (1) symbol speed grade unit -1 -2 -3 min max min max min max t iod 1.2 1.3 1.6 ns t ioc 0.4 0.4 0.5 ns t ioco 0.8 0.9 1.1 ns t iocomb 0.7 0.7 0.8 ns t iosu 2.7 3.1 3.6 ns t ioh 0.2 0.3 0.3 ns t ioclr 1.2 1.3 1.6 ns t od1 3.2 3.6 4.2 ns t od2 5.9 6.7 7.8 ns t od3 8.7 9.8 11.5 ns t xz 3.8 4.3 5.0 ns t zx1 3.8 4.3 5.0 ns t zx2 6.5 7.4 8.6 ns t zx3 9.3 10.5 12.3 ns t inreg 8.2 9.3 10.9 ns t iofd 9.0 10.2 12.0 ns t incomb 9.0 10.2 12.0 ns table 107. epf10k250a device le timing microparameters (part 2 of 2) note (1) symbol speed grade unit -1 -2 -3 min max min max min max
altera corporation 115 flex 10k embedded programmable logic family data sheet table 109. epf10k250a device eab internal microparameters note (1) symbol speed grade unit -1 -2 -3 min max min max min max t eabdata1 1.3 1.5 1.7 ns t eabdata2 1.3 1.5 1.7 ns t eabwe1 0.9 1.1 1.3 ns t eabwe2 5.0 5.7 6.7 ns t eabclk 0.6 0.7 0.8 ns t eabco 0.0 0.0 0.0 ns t eabbypass 0.1 0.1 0.2 ns t eabsu 3.8 4.3 5.0 ns t eabh 0.7 0.8 0.9 ns t aa 4.5 5.0 5.9 ns t wp 5.6 6.4 7.5 ns t wdsu 1.3 1.4 1.7 ns t wdh 0.1 0.1 0.2 ns t wasu 0.1 0.1 0.2 ns t wah 0.1 0.1 0.2 ns t wo 4.1 4.6 5.5 ns t dd 4.1 4.6 5.5 ns t eabout 0.1 0.1 0.2 ns t eabch 2.5 3.0 3.5 ns t eabcl 5.6 6.4 7.5 ns
116 altera corporation flex 10k embedded programmable logic family data sheet table 110. epf10k250a device eab internal timing macroparameters note (1) symbol speed grade unit -1 -2 -3 min max min max min max t eabaa 6.1 6.8 8.2 ns t eabrccomb 6.1 6.8 8.2 ns t eabrcreg 4.6 5.1 6.1 ns t eabwp 5.6 6.4 7.5 ns t eabwccomb 5.8 6.6 7.9 ns t eabwcreg 15.8 17.8 21.0 ns t eabdd 5.7 6.4 7.8 ns t eabdataco 0.7 0.8 1.0 ns t eabdatasu 4.5 5.1 5.9 ns t eabdatah 0.0 0.0 0.0 ns t eabwesu 8.2 9.3 10.9 ns t eabweh 0.0 0.0 0.0 ns t eabwdsu 1.7 1.8 2.1 ns t eabwdh 0.0 0.0 0.0 ns t eabwasu 0.9 0.9 1.0 ns t eabwah 0.0 0.0 0.0 ns t eabwo 5.3 6.0 7.4 ns
altera corporation 117 flex 10k embedded programmable logic family data sheet table 111. epf10k250a device interconnect timing microparameters note (1) symbol speed grade unit -1 -2 -3 min max min max min max t din2ioe 7.8 8.5 9.4 ns t din2le 2.7 3.1 3.5 ns t din2data 1.6 1.6 1.7 ns t dclk2ioe 3.6 4.0 4.6 ns t dclk2le 2.7 3.1 3.5 ns t samelab 0.2 0.3 0.3 ns t samerow 6.7 7.3 8.2 ns t samecolumn 2.5 2.7 3.0 ns t diffrow 9.2 10.0 11.2 ns t tworows 15.9 17.3 19.4 ns t leperiph 7.5 8.1 8.9 ns t labcarry 0.3 0.4 0.5 ns t labcasc 0.4 0.4 0.5 ns table 112. epf10k250a device external reference timing parameters note (1) symbol speed grade -1 -2 -3 unit min max min max min max t drr 15.0 17.0 20.0 ns t insu (2) , (3) 6.9 8.0 9.4 ns t inh (3) 0.0 0.0 0.0 ns t outco (3) 2.0 8.0 2.0 8.9 2.0 10.4 ns
118 altera corporation flex 10k embedded programmable logic family data sheet notes to tables: (1) all timing parameters are described in tables 32 through 38 in this data sheet. (2) using an le to register the signal may provide a lower setup time. (3) this parameter is specified by characterization. clocklock & clockboost timing parameters for the clocklock and clockboost circuitry to function properly, the incoming clock must meet certain requirements. if these specifications are not met, the circuitry may not lock onto the incoming clock, which generates an erroneous clock within the device. the clock generated by the clocklock and clockboost circuitry must also meet certain specifications. if the incoming clock meets these requirements during configuration, the clocklock and clockboost circuitry will lock onto the clock during configuration. the circuit will be ready for use immediately after configuration. figure 31 illustrates the incoming and generated clock specifications. figure 31. speci?ations for the incoming & generated clocks the t i parameter refers to the nominal input clock period; the t o parameter refers to the nominal output clock period. table 113. epf10k250a device external bidirectional timing parameters note (1) symbol speed grade unit -1 -2 -3 min max min max min max t insubidir 9.3 10.6 12.7 ns t inhbidir 0.0 0.0 0.0 ns t outcobidir 2.0 8.0 2.0 8.9 2.0 10.4 ns t xzbidir 10.8 12.2 14.2 ns t zxbidir 10.8 12.2 14.2 ns t r t f t clk1 t induty t i f clkdev t i t i t inclkstb t outduty t o t o + t jitter t o t jitter input clock clocklock- generated clock
altera corporation 119 flex 10k embedded programmable logic family data sheet table 114 summarizes the clocklock and clockboost parameters. notes: (1) to implement the clocklock and clockboost circuitry with the max+plus ii software, designers must specify the input frequency. the max+plus ii software tunes the pll in the clocklock and clockboost circuitry to this frequency. the f clkdev parameter specifies how much the incoming clock can differ from the specified frequency during device operation. simulation does not reflect this parameter. (2) during device configuration, the clocklock and clockboost circuitry is configured before the rest of the device. if the incoming clock is supplied during configuration, the clocklock and clockboost circuitry locks during configuration, because the t lock value is less than the time required for configuration. (3) the t jitter specification is measured under long-term observation. power consumption the supply power (p) for flex 10k devices can be calculated with the following equation: p = p int + p io = (i ccstandby + i ccactive ) v cc + p io typical i ccstandby values are shown as i cc0 in the flex 10k device dc operating conditions tables on pages 44 , 47 , and 50 of this data sheet. the i ccactive value depends on the switching frequency and the application logic. this value is calculated based on the amount of current that each le typically consumes. the p io value, which depends on the device output load characteristics and switching frequency, can be calculated using the guidelines given in application note 74 (evaluating power for altera devices) . table 114. clocklock & clockboost parameters symbol parameter min typ max unit t r input rise time 2ns t f input fall time 2ns t induty input duty cycle 45 55 % f clk1 input clock frequency (clockboost clock multiplication factor equals 1) 30 80 mhz t clk1 input clock period (clockboost clock multiplication factor equals 1) 12.5 33.3 ns f clk2 input clock frequency (clockboost clock multiplication factor equals 2) 16 50 mhz t clk2 input clock period (clockboost clock multiplication factor equals 2) 20 62.5 ns f clkdev1 input deviation from user specification in max+plus ii (clockboost clock multiplication factor equals 1) (1) 1 mhz f clkdev2 input deviation from user specification in max+plus ii (clockboost clock multiplication factor equals 2) (1) 0.5 mhz t inclkstb input clock stability (measured between adjacent clocks) 100 ps t lock time required for clocklock or clockboost to acquire lock (2) 10 s t jitter jitter on clocklock or clockboost-generated clock (3) 1ns t outduty duty cycle for clocklock or clockboost-generated clock 40 50 60 %
120 altera corporation flex 10k embedded programmable logic family data sheet 1 compared to the rest of the device, the embedded array consumes a negligible amount of power. therefore, the embedded array can be ignored when calculating supply current. the i ccactive value is calculated with the following equation: i ccactive = k f max n tog lc the parameters in this equation are shown below: f max = maximum operating frequency in mhz n = total number of logic cells used in the device tog lc = average percent of logic cells toggling at each clock (typically 12.5 % ) k = constant, shown in tables 115 and 116 this calculation provides an i cc estimate based on typical conditions with no output load. the actual i cc should be verified during operation because this measurement is sensitive to the actual pattern in the device and the environmental operating conditions. table 115. flex 10k k constant values device k value epf10k10 82 epf10k20 89 epf10k30 88 epf10k40 92 epf10k50 95 epf10k70 85 epf10k100 88 table 116. flex 10ka k constant values device k value epf10k10a 17 epf10k30a 17 epf10k50v 19 epf10k100a 19 epf10k130v 22 epf10k250a 23 a mhz le -------------------------- -
altera corporation 121 flex 10k embedded programmable logic family data sheet to better reflect actual designs, the power model (and the constant k in the power calculation equations) for continuous interconnect flex devices assumes that logic cells drive fasttrack interconnect channels. in contrast, the power model of segmented fpgas assumes that all logic cells drive only one short interconnect segment. this assumption may lead to inaccurate results, compared to measured power consumption for an actual design in a segmented interconnect fpga. figure 32 shows the relationship between the current and operating frequency of flex 10k devices.
122 altera corporation flex 10k embedded programmable logic family data sheet figure 32. i ccactive vs. operating frequency (part 1 of 3) epf10k20 epf10k10 epf10k40 epf10k30 epf10k50 epf10k70 0 frequency (mhz) 500 450 400 350 300 250 200 150 100 50 30 60 15 45 i cc supply current (ma) 0 frequency (mhz) 1,000 900 800 700 600 500 400 300 200 100 30 60 15 45 i cc supply current (ma) 0 frequency (mhz) 1,600 1,400 1,200 1,000 800 600 400 200 30 60 15 45 i cc supply current (ma) 0 frequency (mhz) 2,500 2,000 1,500 1,000 500 30 60 15 45 i cc supply current (ma) 0 frequency (mhz) 3,000 2,500 2,000 1,500 1,000 500 30 60 15 45 i cc supply current (ma) 30 60 0 frequency (mhz) 15 45 3,500 3,000 2,500 2,000 1,500 1,000 500 i cc supply current (ma)
altera corporation 123 flex 10k embedded programmable logic family data sheet figure 32. i ccactive vs. operating frequency (part 2 of 3) epf10k50v epf10k100 epf10k100a epf10k130v epf10k10a epf10k30a 0 frequency (mhz) 500 1,000 1,500 2,500 2,000 3,000 3,500 4,000 4,500 30 60 15 45 i cc supply current (ma) 0 frequency (mhz) 700 600 500 400 300 200 100 20 40 60 100 80 i cc supply current (ma) 0 frequency (mhz) 20 40 60 100 80 500 1,000 1,500 i cc supply current (ma) 2,000 0 frequency (mhz) 150 100 50 50 100 25 75 i cc supply current (ma) 0 frequency (mhz) 400 300 200 100 50 100 25 75 i cc supply current (ma) 0 frequency (mhz) 20 40 60 100 80 300 600 900 i cc supply current (ma) 1,200
124 altera corporation flex 10k embedded programmable logic family data sheet figure 32. i ccactive vs. operating frequency (part 3 of 3) con?uration & operation the flex 10k architecture supports several configuration schemes. this section summarizes the device operating modes and available device configuration schemes. f see application note 59 (configuring flex 10k devices) for detailed descriptions of device configuration options, device configuration pins, and for information on configuring flex 10k devices, including sample schematics, timing diagrams, and configuration parameters. operating modes the flex 10k architecture uses sram configuration elements that require configuration data to be loaded every time the circuit powers up. the process of physically loading the sram data into the device is called configuration . during initialization, which occurs immediately after configuration, the device resets registers, enables i/o pins, and begins to operate as a logic device. the i/o pins are tri-stated during power-up, and before and during configuration. together, the configuration and initialization processes are called command mode ; normal device operation is called user mode . sram configuration elements allow flex 10k devices to be reconfigured in-circuit by loading new configuration data into the device. real-time reconfiguration is performed by forcing the device into command mode with a device pin, loading different configuration data, reinitializing the device, and resuming user-mode operation. epf10k250a 0 frequency (mhz) 3,500 3,000 2,500 2,000 1,500 1,000 500 20 40 60 100 80 i cc supply current (ma)
altera corporation 125 flex 10k embedded programmable logic family data sheet the entire reconfiguration process may be completed in less than 320 ms using an epf10k250a device with a dclk frequency of 10 mhz. this process can be used to reconfigure an entire system dynamically. in-field upgrades can be performed by distributing new configuration files. programming files despite being function- and pin-compatible, flex 10ka and flex 10ke devices are not programming- or configuration-file compatible with flex 10k devices. a design should be recompiled before it is transferred from a flex 10k device to an equivalent flex 10ka or flex 10ke device. this recompilation should be performed to create a new programming or configuration file and to check design timing on the faster flex 10ka or flex 10ke device. the programming or configuration files for epf10k50 devices can program or configure an epf10k50v device. however, altera recommends recompiling a design for the epf10k50v device when transferring it from the epf10k50 device. con?uration schemes the configuration data for a flex 10k device can be loaded with one of five configuration schemes (see table 117 ), chosen on the basis of the target application. an epc2, epc1, or epc1441 configuration device, intelligent controller, or the jtag port can be used to control the configuration of a flex 10k device, allowing automatic configuration on system power-up. multiple flex 10k devices can be configured in any of the five configuration schemes by connecting the configuration enable ( nce ) and configuration enable output ( nceo ) pins on each device. table 117. data sources for configuration configuration scheme data source configuration device epc2, epc1, or epc1441 configuration device passive serial (ps) bitblaster, byteblaster, or byteblastermv download cable, or serial data source passive parallel asynchronous (ppa) parallel data source passive parallel synchronous (pps) parallel data source jtag bitblaster, byteblaster, or byteblastermv download cable, or microprocessor with jam file or jam byte-code file
126 altera corporation flex 10k embedded programmable logic family data sheet device pin- outs tables 118 through 122 show the pin names and numbers for the dedicated pins in each flex 10k device package. table 118. flex 10k device pin-outs (part 1 of 2) note (1) pin name 84-pin plcc epf10k10 100-pin tqfp epf10k10a 144-pin tqfp epf10k10 epf10k10a epf10k20 epf10k30a 208-pin pqfp/rqfp epf10k10 epf10k10a 208-pin pqfp/ rqfp epf10k20 epf10k30 epf10k30a epf10k40 msel0 (2) 31 54 77 108 108 msel1 (2) 32 53 76 107 107 nstatus (2) 55 25 35 52 52 nconfig (2) 34 51 74 105 105 dclk (2) 13 75 107 155 155 conf_done (2) 761222 init_done (3) 69 10 14 19 19 nce (2) 14 74 106 154 154 nceo (2) 752333 nws (4) 80 97 142 206 206 nrs (4) 81 96 141 204 204 ncs (4) 78 99 144 208 208 cs (4) 79 98 143 207 207 rdynbsy (4) 708 111616 clkusr (4) 73571010 data7 (4) 5 84 116 166 166 data6 (4) 6 82 114 164 164 data5 (4) 7 81 113 162 162 data4 (4) 8 80 112 161 161 data3 (4) 9 79 111 159 159 data2 (4) 10 78 110 158 158 data1 (4) 11 77 109 157 157 data0 (2) , (5) 12 76 108 156 156 tdi (2) 15 73 105 153 153 tdo (2) 743444 tck (2) 77 100 1 1 1 tms (2) 57 24 34 50 50 trst (2) 56 (6) (6) 51 51 dedicated inputs 2, 42, 44, 84 40, 38, 89, 91 54, 56, 124, 126 78, 80, 182, 184 78, 80, 182, 184
altera corporation 127 flex 10k embedded programmable logic family data sheet dedicated clock pins 1, 43 39, 90 55, 125 79, 183 79, 183 dev_clrn (3) 3 87 122 180 180 dev_oe (3) 83 93 128 186 186 vccint 4, 20, 33, 40, 45, 63 18, 37, 52, 66, 88 6, 25, 52, 53, 75, 93, 123 6, 23, 35, 43, 76, 77, 106, 109, 117, 137, 145, 181 6, 23, 35, 43, 76, 77, 106, 109, 117, 137, 145, 181 vccio 4, 17, 32, 49, 67, 83 5, 24, 45, 61, 71, 94, 115, 134 5, 22, 34, 42, 66, 84, 98, 110, 118, 138, 146, 165, 178, 194 5, 22, 34, 42, 66, 84, 98, 110, 118, 138, 146, 165, 178, 194 gndint 26, 41, 46, 68, 82 12, 41, 59, 92 16, 57, 58, 84, 103, 127 21, 33, 49, 81, 82, 123, 129, 151, 185 21, 33, 49, 81, 82, 123, 129, 151, 185 gndio 11, 28, 46, 60, 72, 95 15, 40, 50, 66, 85, 104, 129, 139 20, 32, 48, 59, 72, 91, 124, 130, 152, 171, 188, 201 20, 32, 48, 59, 72, 91, 124, 130, 152, 171, 188, 201 no connect (n.c.) (7) 7, 8, 9, 14, 15, 36, 37, 113, 114, 125, 126, 139, 140 total user i/o pins (8) 59 66 102 134 147 table 118. flex 10k device pin-outs (part 2 of 2) note (1) pin name 84-pin plcc epf10k10 100-pin tqfp epf10k10a 144-pin tqfp epf10k10 epf10k10a epf10k20 epf10k30a 208-pin pqfp/rqfp epf10k10 epf10k10a 208-pin pqfp/ rqfp epf10k20 epf10k30 epf10k30a epf10k40
128 altera corporation flex 10k embedded programmable logic family data sheet table 119. flex 10k device pin-outs (part 1 of 2) note (1) pin name 240-pin pqfp/rqfp epf10k20 epf10k30 epf10k30a epf10k40 epf10k50 epf10k50v epf10k70 epf10k100a 256-pin fineline bga epf10k10a 256-pin fineline bga epf10k30a msel0 (2) 124 p1 p1 msel1 (2) 123 r1 r1 nstatus (2) 60 t16 t16 nconfig (2) 121 n4 n4 dclk (2) 179 b2 b2 conf_done (2) 2 c15 c15 init_done (3) 26 g16 g16 nce (2) 178 b1 b1 nceo (2) 3 b16 b16 nws (4) 238 b14 b14 nrs (4) 236 c14 c14 ncs (4) 240 a16 a16 cs (4) 239 a15 a15 rdynbsy (4) 23 g14 g14 clkusr (4) 11 d15 d15 data7 (4) 190 b5 b5 data6 (4) 188 d4 d4 data5 (4) 186 a4 a4 data4 (4) 185 b4 b4 data3 (4) 183 c3 c3 data2 (4) 182 a2 a2 data1 (4) 181 b3 b3 data0 (2) , (5) 180 a1 a1 tdi (2) 177 c2 c2 tdo (2) 4 c16 c16 tck (2) 1 b15 b15 tms (2) 58 p15 p15 trst (2) 59 r16 r16 dedicated inputs 90, 92, 210, 212 b9, e8, m9, r8 b9, e8, m9, r8
altera corporation 129 flex 10k embedded programmable logic family data sheet dedicated clock pins 91, 211 a9, l8 a9, l8 dev_clrn (3) 209 d8 d8 dev_oe (3) 213 c9 c9 vccint 5, 16, 27, 37, 47, 57, 77, 89, 96, 112, 122, 130, 140, 150, 160, 170, 189, 205, 224 e11, f5, f7, f9, f12, h6, h7, h10, j7, j10, j11, k9, l5, l7, l9, l12, m11, r2 e11, f5, f7, f9, f12, h6, h7, h10, j7, j10, j11, k9, l5, l7, l9, l12, m11, r2 vccio (16) d12, e6, f8, f10, g6, g8, g11, h11, j6, k6, k8, k11, l10, m6, n12 d12, e6, f8, f10, g6, g8, g11, h11, j6, k6, k8, k11, l10, m6, n12 gndint 10, 22, 32, 42, 52, 69, 85, 93, 104, 125, 135, 145, 155, 165, 176, 197, 216, 232 e5, e12, f6, f11, g7, g9, g10, h8, h9, j8, j9, k7,k10, l6, l11, m5, m12, t8 e5, e12, f6, f11, g7, g9, g10, h8, h9, j8, j9, k7,k10, l6, l11, m5, m12, t8 gndio no connect (n.c.) a8, b8, d1, d14, d16, e1, e3, e13, e14, e15, e16, f14, f15, f16, g3, h1, h4, h16, j1, j2, k2, k3, k12, k14, k15, k16, l2, l4, m2, m3, m4, m14, m16, n1, n2, n3, n14, n15, p2, p11, p14 (7) total user i/o pins (8) 189 150 191 table 119. flex 10k device pin-outs (part 2 of 2) note (1) pin name 240-pin pqfp/rqfp epf10k20 epf10k30 epf10k30a epf10k40 epf10k50 epf10k50v epf10k70 epf10k100a 256-pin fineline bga epf10k10a 256-pin fineline bga epf10k30a
130 altera corporation flex 10k embedded programmable logic family data sheet table 120. flex 10k device pin-outs (part 1 of 2) note (1) pin name 356-pin bga epf10k30 epf10k30a 356-pin bga epf10k50 epf10k50v epf10k100a 403-pin pga epf10k50 msel0 (2) d4 d4 an1 msel1 (2) d3 d3 ar1 nstatus (2) d24 d24 au37 nconfig (2) d2 d2 au1 dclk (2) ac5 ac5 e1 conf_done (2) ac24 ac24 c37 init_done (3) t24 t24 r35 nce (2) ac2 ac2 g1 nceo (2) ac22 ac22 e37 nws (4) ae24 ae24 e31 nrs (4) ae23 ae23 a33 ncs (4) ad24 ad24 a35 cs (4) ad23 ad23 c33 rdynbsy (4) u22 u22 n35 clkusr (4) aa24 aa24 g35 data7 (4) af4 af4 c9 data6 (4) ad8 ad8 a7 data5 (4) ae5 ae5 e9 data4 (4) ad6 ad6 c7 data3 (4) af2 af2 a5 data2 (4) ad5 ad5 e7 data1 (4) ad4 ad4 c5 data0 (2) , (5) ad3 ad3 c1 tdi (2) ac3 ac3 j1 tdo (2) ac23 ac23 g37 tck (2) ad25 ad25 a37 tms (2) d22 d22 an37 trst (2) d23 d23 ar37 dedicated inputs a13, b14, af14, ae13, a13, b14, af14, ae13 a17, a21, au17, au21 dedicated clock pins a14, af13 a14, af13 a19, au19 dev_clrn (3) ad13 ad13 c17 dev_oe (3) ae14 ae14 c19
altera corporation 131 flex 10k embedded programmable logic family data sheet vccint a1, a26, c14, c26, d5, f1, h22, j1, m26, n1, t26, u5, aa1, ad26, af1, af26 a1, a26, c14, c26, d5, f1, h22, j1, m26, n1, t26, u5, aa1, ad26, af1, af26 b2, d14, e25, f22, k36, t2, t32, v6, ad34, ae5, al5, am6, am20, an25, an29, ap4, at16, at36 vccio a7, a23, b4, c15, d25, f4, h24, k5, m23, p2, t25, v2, w22, ab1, ac25, ad18, af3, af7, af16 a7, a23, b4, c15, d25, f4, h24, k5, m23, p2, t25, v2, w22, ab1, ac25, ad18, af3, af7, af16 b22, d34, e11, e27, f16, l5, l33, p4, t6, t36, v32, ab36, ag5, ag33, ah2, am18, am32, an11, an27, ap24, at22 gndint a2, a10, a20, b1, b13, b22, b25, b26, c2, c9, c13, c25, h23, j26, k1, m1, n26, r1, r26, t1, u26, w1, ad2, ad14, ad20, ae1, ae2, ae7, ae25, ae26, af11, af19, af25 a2, a10, a20, b1, b13, b22, b25, b26, c2, c9, c13, c25, h23, j26, k1, m1, n26, r1, r26, t1, u26, w1, ad2, ad14, ad20, ae1, ae2, ae7, ae25, ae26, af11, af19, af25 b16, b36, d4, e21, f18, f32, g33, p34, u5, y32, aa33, ab2, ab6, ah36, am16, an17, an21, ap14, at2 gndio b10, b28, d24, e5, e19, e33, f6, f20, k2, w5, w33, y6, ab32, ad4, am22, an5, an19, an33, ap34, at10, at28 no connect (n.c.) c1, d1, d26, e1, e2, g1, g5, g23, g26, h1, h25, h26, j25, k25, p24, r24, t23, u25, v1, v3, v4, v26, w2, w3, y1, y2, y23, ac26 (9) total user i/o pins (8) 246 274 310 table 120. flex 10k device pin-outs (part 2 of 2) note (1) pin name 356-pin bga epf10k30 epf10k30a 356-pin bga epf10k50 epf10k50v epf10k100a 403-pin pga epf10k50
132 altera corporation flex 10k embedded programmable logic family data sheet table 121. flex 10k pin-outs (part 1 of 3) note (1) pin name 484-pin fineline bga epf10k30a 484-pin fineline bga epf10k50v 484-pin fineline bga epf10k100a 503-pin pga epf10k70 msel0 (2) u4 u4 u4 at40 msel1 (2) v4 v4 v4 av40 nstatus (2) w19 w19 w19 ay4 nconfig (2) t7 t7 t7 ay40 dclk (2) e5 e5 e5 h40 conf_done (2) f18 f18 f18 f4 init_done (3) k19 k19 k19 v6 nce (2) e4 e4 e4 k40 nceo (2) e19 e19 e19 h4 nws (4) e17 e17 e17 a3 nrs (4) f17 f17 f17 c5 ncs (4) d19 d19 d19 c1 cs (4) d18 d18 d18 c3 rdynbsy (4) k17 k17 k17 t6 clkusr (4) g18 g18 g18 h6 data7 (4) e8 e8 e8 e29 data6 (4) g7 g7 g7 d30 data5 (4) d7 d7 d7 c31 data4 (4) e7 e7 e7 b32 data3 (4) f6 f6 f6 d32 data2 (4) d5 d5 d5 b34 data1 (4) e6 e6 e6 e33 data0 (2) , (5) d4 d4 d4 f40 tdi (2) f5 f5 f5 m40 tdo (2) f19 f19 f19 k4 tck (2) e18 e18 e18 d4 tms (2) u18 u18 u18 at4 trst (2) v19 v19 v19 av4 dedicated inputs e12, h11, r12, v11 e12, h11, r12, v11 e12, h11, r12, v11 d20, d24, ay24, ay20 dedicated clock pins d12, p11 d12, p11 d12, p11 d22, ay22 dev_clrn (3) g11 g11 g11 f22 dev_oe (3) f12 f12 f12 g21
altera corporation 133 flex 10k embedded programmable logic family data sheet vccint c11, c15, h14, j8, j10, j12, j15, l9, l10, l13, m10, m13, m14, n12, p8, p10, p12, p15, r14, v5, w21, y8, aa12 c11, c15, h14, j8, j10, j12, j15, l9, l10, l13, m10, m13, m14, n12, p8, p10, p12, p15, r14, v5, w21, y8, aa12 c11, c15, h14, j8, j10, j12, j15, l9, l10, l13, m10, m13, m14, n12, p8, p10, p12, p15, r14, v5, w21, y8, aa12 c11, e39, g27, n5, n41, w39, ac3, ag7, ar3, ar41, au37, aw5, aw25, aw41, ba17, ba19 vccio a6, a13, b5, e1, g1, g15, h9, h20, j11, j13, k9, k11, k14, k20, l14, m9, n3, n9, n11, n14, n20, p13, r1, r9, t3, t15, t22, v22, ab13 a6, a13, b5, e1, g1, g15, h9, h20, j11, j13, k9, k11, k14, k20, l14, m9, n3, n9, n11, n14, n20, p13, r1, r9, t3, t15, t22, v22, ab13 a6, a13, b5, e1, g1, g15, h9, h20, j11, j13, k9, k11, k14, k20, l14, m9, n3, n9, n11, n14, n20, p13, r1, r9, t3, t15, t22, v22, ab13 c9, c15, c25, c33, c37, e19, e41, g7, l3, r41, u3, u37, w5, ac41, ae5, aj41, al39, au3, au17, aw3, aw19, ba9, ba27, ba29, ba37 gndint a1, a8, a22, b1, b2, b17, b21, b22, c2, c21, e21, g3, g21, h2, h8, h15, j9, j14, j20, k3, k10, k12, k13, l11, l12, m11, m12, m20, n10, n13, p9, p14, r8, r15, r22, t1, v3, w11, w20, y1, y2, y3, y21, y22, aa1, aa6, aa22, ab11, ab16 a1, a8, a22, b1, b2, b17, b21, b22, c2, c21, e21, g3, g21, h2, h8, h15, j9, j14, j20, k3, k10, k12, k13, l11, l12, m11, m12, m20, n10, n13, p9, p14, r8, r15, r22, t1, v3, w11, w20, y1, y2, y3, y21, y22, aa1, aa6, aa22, ab11, ab16 a1, a8, a22, b1, b2, b17, b21, b22, c2, c21, e21, g3, g21, h2, h8, h15, j9, j14, j20, k3, k10, k12, k13, l11, l12, m11, m12, m20, n10, n13, p9, p14, r8, r15, r22, t1, v3, w11, w20, y1, y2, y3, y21, y22, aa1, aa6, aa22, ab11, ab16 c17, e3, e5, e25, g37, j3, j41, u7, aa3, ae39, al5, al41, au27, aw39, ba7, ba13, ba25 gndio c21, c23, c39, c41, e13, e31, g3, g17, n3, n39, r3, w41, w3, aa41, ag37, aj3, an3, an41, au7, au41, aw13, aw31, ba11, ba21, ba23 table 121. flex 10k pin-outs (part 2 of 3) note (1) pin name 484-pin fineline bga epf10k30a 484-pin fineline bga epf10k50v 484-pin fineline bga epf10k100a 503-pin pga epf10k70
134 altera corporation flex 10k embedded programmable logic family data sheet no connect (n.c.) a2, a3, a4, a5, a7, a9, a11, a12, a14, a15, a20, a21, b3, b4, b9, b10, b12, b16, b19, b20, c1, c6, c9, c10, c12, c13, c14, c16, c17, c22, d1, d2, d3, d20, d21, e2, e3, e20, e22, f1, f2, f3, f20, f21, g2, g20, g22, h3, j1, j2, j3, j21, j22, k2, k22, l1, l2, l3, l20, l21, l22, m2, m3, m21, m22, n1, n2, n21, n22, p2, p3, p20, p21, p22, r2, r3, r20, r21, t2, t20, t21, u1, u2, u3, u20, u21, u22, v2, v20, w1, w2, w22, y4, y9, y12, y13, y16, y19, y20, aa2, aa3, aa4, aa9, aa11, aa13, aa15, aa21, ab1, ab2, ab3, ab4, ab5, ab7, ab8, ab9, ab12, ab15, ab17, ab18, ab19, ab20, ab21, ab22 (9) a2, a3, a4, a5, a7, a9, a11, a12, a14, a15, a20, a21, b3, b4, b9, b10, b12, b16, b19, b20, c1, c6, c9, c10, c12, c13, c14, c16, c17, d1, d2, d3, d20, e20, f2, j2, k2, l2, n1, p20, p22, r3, t20, t21, u1, u3, w22, y4, y9, y12, y13, y16, y19, y20, aa2, aa3, aa4, aa9, aa11, aa13, aa15, aa21, ab1, ab2, ab3, ab4, ab5, ab7, ab8, ab9, ab12, ab15, ab17, ab18, ab19, ab20, ab21, ab22 (10) a19, a21, a23, a31, a33, a35, a39, a41, b16, b18, b22, b24, b30, b40, c29, c35, d18, d26, d28, d38, e27, e37, f18, f2, f26, f30, f32, g23, g25, g29, g31, g33, g35, k6, k42, l39, l43, m2, n7, p38, p4, p42, r37, t40, v42, ac5, ad2, ae3 (11) total user i/o pins (8) 246 291 369 358 table 121. flex 10k pin-outs (part 3 of 3) note (1) pin name 484-pin fineline bga epf10k30a 484-pin fineline bga epf10k50v 484-pin fineline bga epf10k100a 503-pin pga epf10k70
altera corporation 135 flex 10k embedded programmable logic family data sheet table 122. flex 10k pin-outs (part 1 of 3) note (1) pin name 503-pin pga epf10k100 599-pin pga epf10k130v epf10k250a 600-pin bga epf10k100a 600-pin bga epf10k130v epf10k250a msel0 (2) at40 f6 f5 f5 msel1 (2) av40 c3 c1 c1 nstatus (2) ay4 e43 d32 d32 nconfig (2) ay40 b4 d4 d4 dclk (2) h40 be5 ap1 ap1 conf_done (2) f4 bc43 am32 am32 init_done (3) v6 am40 ae32 ae32 nce (2) k40 bb6 an2 an2 nceo (2) h4 bf44 ap35 ap35 nws (4) a3 bb40 ar29 ar29 nrs (4) c5 ba37 am28 am28 ncs (4) c1 ay38 al29 al29 cs (4) c3 ba39 an29 an29 rdynbsy (4) t6 aw47 ag35 ag35 clkusr (4) h6 ay42 am34 am34 data7 (4) e29 bd14 am13 am13 data6 (4) d30 ba17 ar12 ar12 data5 (4) c31 bb16 an12 an12 data4 (4) b32 bf12 ap11 ap11 data3 (4) d32 bg11 am11 am11 data2 (4) b34 bg9 ar10 ar10 data1 (4) e33 bf10 an10 an10 data0 (2) , (5) f40 bc5 am4 am4 tdi (2) m40 bf4 an1 an1 tdo (2) k4 bb42 an34 an34 tck (2) d4 be43 al31 al31 tms (2) at4 f42 c35 c35 trst (2) av4 b46 c34 c34 dedicated inputs d20, d24, ay24, ay20 b24, c25, bg25, bg23 c18, d18, am18, an18 c18, d18, am18, an18 dedicated clock pins d22, ay22 bf24, a25 al18, e18 al18, e18 lock (12) av14 gclk1 (13) ay22 dev_clrn (3) f22 be23 ar17 ar17
136 altera corporation flex 10k embedded programmable logic family data sheet dev_oe (3) g21 bc25 ar19 ar19 vccint c11, e39, g27, n5, n41, w39, ac3, ag7, ar3, ar41, au37, aw5, aw25, aw41, ba17 a3, a45, c1, c11, c19, c29, c37, c47, e5, g25, l3, l45, w3, w45, aj3, aj45, au3, au45, be1, be11, be19, be29, be37, be47, bg3, bg45 a11, a19, b1, b18, d24, e2, f31, f35, h1, k32, m2, n34, p5, t35, u3, v32, y2, aa33, ab5, ad35, ae4, af32, ag5, ak31, ak35, al3, ap24, ar11, ar18 a11, a19, b1, b18, d24, e2, f31, f35, h1, k32, m2, n34, p5, t35, u3, v32, y2, aa33, ab5, ad35, ae4, af32, ag5, ak31, ak35, al3, ap24, ar11, ar18 vccio c9, c15, c25, c33, c37, e19, e41, g7, l3, r41, u3, u37, w5, ac41, ae5, aj41, al39, au3, au17, aw3, aw19, ba9, ba27, ba29, ba37 d24, e9, e15, e21, e27, e33, e39, g7, g41, j5, j43, r5, r43, aa5, aa43, ad4, ad44, ag5, ag43, an5, an43, aw5, aw43, ba7, ba41, bc9, bc15, bc21, bc27, bc33, bc39, bd24 a20, a27, c2, c3, c4, c8, c15, c23, c32, c33, d5, d31, e5, e12, e31, al5, al12, am5, am19, am26, am31, an3, an4, an8, an15, an32, an33, ap34, ar23 a20, a27, c2, c3, c4, c8, c15, c23, c32, c33, d5, d31, e5, e12, e31, al5, al12, am5, am19, am26, am31, an3, an4, an8, an15, an32, an33, ap34, ar23 vcc_cklk (14) ba19 gndint c17, e3, e5, e25, g37, j3, j41, u7, aa3, ae39, al5, al41, au27, aw39, ba7, ba13 a47, b2, c13, c21, c27, c35, c45, d4, g23, n3, n45, aa3, aa45, ag3, ag45, ar3, ar45, bd44, be3, be13, be21, be27, be35, be45, bg1, bg47 a1, a2, a3, a4, a5, a18, a31, a32, a33, a34, a35, b2, b3, b4, b5, b6, b31, b32, b33, b34, b35, c5, c6, c30, c31, d6, d30, e6, an35 a1, a2, a3, a4, a5, a18, a31, a32, a33, a34, a35, b2, b3, b4, b5, b6, b31, b32, b33, b34, b35, c5, c6, c30, c31, d6, d30, e6, an35 gndio c21, c23, c39, c41, e13, e31, g3, g17, n3, n39, r3, w3, w41, aa41, ag37, aj3, an3, an41, au7, au41, aw13, aw31, ba11, ba23, ba21 e7, e13, e19, e29, e35, e41, f24, g5, g43, h40, n5, n43, w5, w43, ad6, ad42, aj5, aj43, ar5, ar43, ay8, ay40, ba5, ba43, bb24, bc7, bc13, bc19, bc29, bc35, bc41 e30, al6, al30, am6, am30, an5, an6, an30, an31, ap2, ap3, ap4, ap5, ap6, ap30, ap31, ap32, ap33, ar1, ar2, ar3, ar4, ar5, ar30, ar31, ar32, ar33, ar34, ar35 e30, al6, al30, am6, am30, an5, an6, an30, an31, ap2, ap3, ap4, ap5, ap6, ap30, ap31, ap32, ap33, ar1, ar2, ar3, ar4, ar5, ar30, ar31, ar32, ar33, ar34, ar35 gnd_cklk (14) ba25 table 122. flex 10k pin-outs (part 2 of 3) note (1) pin name 503-pin pga epf10k100 599-pin pga epf10k130v epf10k250a 600-pin bga epf10k100a 600-pin bga epf10k130v epf10k250a
altera corporation 137 flex 10k embedded programmable logic family data sheet notes to tables: (1) all pins that are not listed are user i/o pins. (2) this pin is a dedicated pin; it is not available as a user i/o pin. (3) this pin can be used as a user i/o pin if it is not used for its device-wide or configuration function. (4) this pin can be used as a user i/o pin after configuration. (5) this pin is tri-stated in user mode. (6) the optional jtag pin trst is not used in the 100-pin or 144-pin tqfp package. (7) to maintain pin compatibility when transferring to the epf10k10 or epf10k10a device from any other device in the 208-pin pqfp or 256-pin fineline bga package, do not use these pins as user i/o pins. (8) the user i/o pin count includes dedicated input pins, dedicated clock pins, and all i/o pins. (9) to maintain pin compatibility when transferring to the epf10k30 device from any other device in the 356-pin bga or 484-pin fineline bga package, do not use these pins as user i/o pins. (10) to maintain pin compatibility when transferring to the epf10k50v device from any other device in the 484-pin fineline bga package, do not use these pins as user i/o pins. (11) to maintain pin compatibility when transferring from the epf10k100 to the epf10k70 in the 503-pin pga package, do not use these pins as user i/o pins. (12) this pin shows the status of the clocklock and clockboost circuitry. when the clocklock and clockboost circuitry are locked to the incoming clock and generate an internal clock, lock is driven high. lock remains high if a periodic clock stops clocking. the lock function is optional; if the lock output is not used, this pin is a user i/o pin. (13) this pin drives the clocklock and clockboost circuitry. (14) this pin is the power or ground for the clocklock and clockboost circuitry. to ensure noise resistance, the power and ground supply to the clocklock and clockboost circuitry should be isolated from the power and ground to the rest of the device. (15) to maintain pin compatibility when transferring to the epf10k100a device from another device in the 600-pin bga package, do not use these pins as user i/o pins. no connect (n.c.) d1, d2, d3, e1, e3, e4, e32, f1, f2, f3, f4, g1, g2, g3, g4, g5, h5, d33, d34, d35, e33, e34, e35, f32, f33, f34, g31, g32, g33, g34, g35, h31, ab31, ab32, ab33, ab34, ac31, ac32, ac33, ac34, ac35, ad31, ad32, ad33, ad34, ae33, ae34, ae35, ah5, aj2, aj3, aj4, aj5, ak1, ak2, ak3, ak4, ak5, al1, al2, al4, am1, am2, am3 (15) total user i/o pins (8) 406 470 406 470 table 122. flex 10k pin-outs (part 3 of 3) note (1) pin name 503-pin pga epf10k100 599-pin pga epf10k130v epf10k250a 600-pin bga epf10k100a 600-pin bga epf10k130v epf10k250a
138 altera corporation flex 10k embedded programmable logic family data sheet (16) the 240 pin qfp packages do not support the multivolt i/o feature so there are no v ccio pins.
altera corporation 139 flex 10k embedded programmable logic family data sheet revision history the information contained in the flex 10k embedded programmable logic family data sheet version 4.02 supersedes information published in previous versions. version 4.02 the following changes were made to the flex 10k embedded programmable logic family data sheet version 4.02: added additional text to note (2) on page 51 . added note (1) to figure 13 on page 29 . added note (1) to table 12 on page 39 . added note (16) to table 119 on page 128 . updated figure 26 on page 56 . version 4.01 the following changes were made to the flex 10k embedded programmable logic family data sheet version 4.01: updated information on the chip-wide output enable and chip-wide reset pins in the i/o element section on page 32 . updated note (2) on page 45 .
140 altera corporation flex 10k embedded programmable logic family data sheet 101 innovation drive san jose, ca 95134-2020 (408) 544-7000 applications hotline: (800) 800-epld customer marketing: (408) 544-7104 literature services: (408) 544-7144 altera, max, max+plus, max+plus ii, ahdl, flex 10k, flex 10ka, flex 10ke, multivolt, bitblaster, byteblaster, byteblastermv, epf10k10, epf10k10a, epf10k20, epf10k30, epf10k30a, epf10k40, epf10k50, epf10k50v, epf10k70, epf10k100, epf10k100a, epf10k130v, epf10k250a, clocklock, clockboost, and fasttrack interconnect are trademarks and/or service marks of altera corporation in the united states and other countries. altera products are protected under numerous u.s. and foreign patents and pending applications, maskwork rights, and copyrights. altera warrants performance of its semiconductor products to current specifications in accordance with altera? standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera corporation. altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. copyright ? 2000 altera corporation. all rights reserved.

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